A40MX04-PLG44 Actel, A40MX04-PLG44 Datasheet - Page 29

• Manufacturer Part Number: A40MX04-PLG44
• Description: FPGA - Field Programmable Gate Array 6K System Gates
• Manufacturer: Actel

Specifications of A40MX04-PLG44

• Processor Series: A40MX04
• Core: IP Core
• Number Of Macrocells: 547
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 69
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 6000
• Package / Case: PLCC-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timing Models
Note:
Figure 1-17 • 40MX Timing Model*
Notes: *Values are shown for A42MX09 ‘–3’ at 5.0V worst-case commercial conditions.
Figure 1-18 • 42MX Timing Model*
† Input module predicted routing delay.
* Values are shown for 40MX ‘–3’ speed devices at 5.0V worst-case commercial conditions.
Array
Clock
Clocks
Array
I/O Module
I/O Module
t
t INSU=0.3 ns
t INGL=1.3 ns
INH=0.0 ns
F MAX=296 MHz
t
CKH=2.70 ns
F MAX=180 MHz
t CKH=4.55 ns
Input Delays
Input Delay
D
G
t INYL=0.62 ns t
t INYL=0.8 ns
Q
FO = 32
t IRD1=2.09 ns
t IRD4=3.64 ns
t IRD8=5.73 ns
t
IRD2=2.59 ns
IRD1=2.0 ns
FO=128
t SUD=0.3 ns
t
HD=0.00 ns
†
t LCO=5.2 ns (light loads, pad-to-pad)
Combin
-atoria l
include
Internal Delays
Logic
Combinatorial
Internal Delays
Logic Module
t PD=1.2 ns
Logic Module
t PD=1.24 ns
t CO=1.24 ns
Logic Module
Sequential
v6.1
t CO=1.3 ns
D
t RD1=1.28 ns
t RD2=1.80 ns
t RD4=2.33 ns
t RD8=4.93 ns
Q
t
t RD2=1.9 ns
t
t RD8=2.3 ns
Predicted
Predicted
RD1=0.7 ns
RD4=1.4 ns
Routing
Routing
Delays
Delays
t RD1=0.70 ns
I/O Module
I/O Module
I/O Module
t
t OUTSU=0.3 ns
t GLH=2.6 ns
OUTH=0.00 ns
Output Delay
D
Output Delays
G
t ENHZ=7.92 ns
t DLH=3.32 ns
Q
t DLH=2.5 ns
t DLH=2.5 ns
40MX and 42MX FPGA Families
t ENHZ=4.9 ns
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