A40MX04-PLG44 Actel, A40MX04-PLG44 Datasheet - Page 15

• Manufacturer Part Number: A40MX04-PLG44
• Description: FPGA - Field Programmable Gate Array 6K System Gates
• Manufacturer: Actel

Specifications of A40MX04-PLG44

• Processor Series: A40MX04
• Core: IP Core
• Number Of Macrocells: 547
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 69
• Delay Time: 5.6 ns
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 3 V
• Number Of Gates: 6000
• Package / Case: PLCC-44
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

C
C
C
C
C
f
f
f
f
f
Fixed Capacitance Values for MX FPGAs (pF)
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-
in access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nets of the device while it is operating in a
prototyping or a production system. The user can probe
into an MX device without changing the placement and
routing of the design and without using any additional
Figure 1-12 • Silicon Explorer II Setup with 40MX
m
n
p
q1
q2
EQM
EQI
EQO
EQCR
L
Device Type
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
= Equivalent capacitance of routed array clock in
= Output load capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz
= Average second routed array clock rate in MHz
pF
r
routed_Clk1
41.4
68.6
118
165
185
220
Serial Connection
1
to Windows PC
16 Logic Analyzer Channels
r
routed_Clk2
N/A
N/A
118
165
185
220
2
Explorer II
Silicon
v6.1
PRB
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
Silicon
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification
verification time from several hours per cycle to a few
seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Figure 1-12
Silicon Explorer II and 40MX devices, while
on page 1-10
Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to <zBlue>“User Security”
section on page 6 for the security fuses of 40MX and
42MX devices).
possible device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the
"Reserve
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
PRA
MODE
DCLK
SDO
SDI
Explorer
Probe
illustrates the interconnection between
process
illustrates the interconnection between
Table 2 on page 1-10
II
40MX
Pin"
at
samples
40MX and 42MX FPGA Families
their
is
data
desks
checked
summarizes the
at
and
Figure 1-13
100
in
reduces
MHz
the
1-9