A40MX04-PLG44 Actel, A40MX04-PLG44 Datasheet - Page 12
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A40MX04-PLG44
Manufacturer Part Number
A40MX04-PLG44
Description
FPGA - Field Programmable Gate Array 6K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A40MX04-PLG44
Processor Series
A40MX04
Core
IP Core
Number Of Macrocells
547
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
69
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
6000
Package / Case
PLCC-44
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A40MX04-PLG44I
Manufacturer:
Microsemi SoC
Quantity:
10 000
MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0V,
3.3V, and mixed 3.3V/5.0V operations.
The MultiPlex I/O modules provide the interface between
the device pins and the logic array.
diagram of the 42MX I/O module. A variety of user
functions, determined by a library macro selection, can
be implemented in the module. (Refer to the
Macro Library Guide
modules contain tristate buffers, with input and output
latches that can be configured for input, output, or
bidirectional operation.
All 42MX devices contain flexible I/O structures, where
each output pin has a dedicated output-enable control
(Figure
output data, or both, providing fast set-up time. In
addition, the Actel Designer software tools can build a D-
type flip-flop using a C-module combined with an I/O
module to register input and output signals. Refer to the
Antifuse Macro Library Guide
A42MX24 and A42MX36 devices also offer selectable PCI
output drives, enabling 100% compliance with version
2.1 of the PCI specification. For low-power systems, all
inputs and outputs are turned off to reduce current
consumption to below 500μA.
To achieve 5.0V or 3.3V PCI-compliant output drives on
A42MX24 and A42MX36 devices, a chip-wide PCI fuse is
programmed via the Device Selection Wizard in the
Designer software
programmed, the output drive is standard.
Actel's Designer software development tools provide a
design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
Note: *Can be configured as a Latch or D Flip-Flop (Using
Figure 1-9 • 42MX I/O Module
1 -6
40MX and 42MX FPGA Families
C-Module)
1-9). The I/O module can be used to latch input or
To Array
From Array
(Figure
for more information.) All 42MX I/O
Q
Q
G/CLK*
G/CLK*
1-10). When the PCI fuse is not
D
D
for more details.
EN
Figure 1-9
PAD
is a block
Antifuse
v6.1
Figure 1-10 • PCI Output Structure of A42MX24 and
A42MX36 Devices
Other Architectural Features
Performance
MX devices can operate with internal clock frequencies
of 250 MHz, enabling fast execution of complex logic
functions. MX devices are live on power-up and do not
require auxiliary configuration devices and thus are an
optimal
contained in multiple programmable logic devices. In
addition, designs that previously would have required a
gate array to meet performance can be integrated into
an MX device with improvements in cost and time-to-
market. Using timing-driven place-and-route (TDPR)
tools, designers can achieve highly deterministic device
performance.
User Security
The Actel FuseLock provides robust security against
design theft. Special security fuses are hidden in the
fabric of the device and prevent unauthorized users from
accessing the programming and/or probe interfaces. It is
virtually impossible to identify or bypass these fuses
without damaging the device, making Actel antifuse
FPGAs immune to both invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe
Fuse and Program Fuse. The former disables the probing
circuitry while the latter prohibits further programming
of all fuses, including the Probe Fuse. In 42MX devices,
there is the Security Fuse which, when programmed,
both disables the probing circuitry and prohibits further
programming of the device.
Look for this symbol to ensure your valuable IP is secure.
For more information, refer to
Security in Actel Antifuse FPGAs
Signal
platform
PCI Enable
Fuse
to
integrate
STD
PCI
Drive
Actel's Implementation of
application note.
the
Output
functionality