A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 72

• Manufacturer Part Number: A2F200M3F-1FGG256
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG256

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SmartFusion DC and Switching Characteristics
2- 60
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the
global clock delays for the A2F200 device. Minimum and maximum delays are measured with minimum
and maximum loading.
Timing Characteristics
Table 2-79 • A2F500 Global Resource
Table 2-80 • A2F200 Global Resource
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage-supply levels, refer to
Parameter
t
t
t
t
t
F
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
3. For specific junction temperature and voltage-supply levels, refer to
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RCKL
RCKH
RCKMPWH
RCKMPWL
RCKSW
RMAX
RMAX
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
element, located in a lightly loaded row (single element is connected to the global net).
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
values.
"Clock Conditioning Circuits" section on page
Worst Commercial-Case Conditions: T
Worst Commercial-Case Conditions: T
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
Description
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
Maximum Frequency for Global Clock
R e visio n 6
2-63.
J
J
= 85°C, VCC = 1.425 V
= 85°C, VCC = 1.425 V
Table 2-80
Min.
Min.
1.54
1.53
0.74
0.76
1
1
–1
–1
presents minimum and maximum
Max.
Table 2-7 on page 2-9
Max.
Table 2-7 on page 2-9
1.73
1.76
0.23
0.99
1.05
0.29
2
2
Min.
Min.
1.84
1.84
0.88
0.91
1
1
Std.
Std.
Max.
Max.
2.08
0.28
1.19
0.35
2.12
1.26
for derating
for derating
2
2
Units
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns