A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 58
![FPGA - Field Programmable Gate Array 200K System Gates SmartFusion](/photos/16/14/161496/lpsilverchip_sml.jpg)
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
ACT
Quantity:
36
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F200M3F-1FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
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SmartFusion DC and Switching Characteristics
Figure 2-15 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
2- 46
Enable
Data
CLK
CLR
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
CC
BB
AA
DD
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
D
E
DFN1E1C1
CLR
Q
EE
INBUF
Y
R e visio n 6
Array
Core
INBUF
CLKBUF
Data_out
LL
HH
JJ
KK
GG
FF
Data Output Register and
Enable Output Register with
D
E
D
E
DFN1E1C1
DFN1E1C1
Active High Enable
Active High Clear
Positive-Edge Triggered
CLR
CLR
Q
Q
DOUT
EOUT
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