A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 15

FPGA - Field Programmable Gate Array 200K System Gates SmartFusion

A2F200M3F-1FGG256

Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet

Specifications of A2F200M3F-1FGG256

Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Table 2-3 • Recommended Operating Conditions
Symbol
T
VCC
VJTAG
VPP
VCCPLLx
VCCFPGAIOBx/
VCCMSSIOBx
VCC33A
VCC33ADCx
VCC33AP
VCC33SDDx
VAREFx
VCCRCOSC
VDDBAT
VCCMAINXTAL
VCCLPXTAL
VCCENVM
VCCESRAM
VCC15A
VCC15ADCx
Notes:
1. All parameters representing voltages are measured with respect to GND unless otherwise specified.
2. The following 1.5 V supplies should be connected together while following proper noise filtering practices: VCC,
3. VPP can be left floating during operation (not programming mode).
4. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O
5. The following 3.3 V supplies should be connected together while following proper noise filtering practices: VCC33A,
J
VCC15A, and VCC15ADCx.
standard are given in
VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL, and VCCLPXTAL.
2
5
2
5
5
5
5
2
4
5
Junction temperature
1.5 V DC core supply voltage
JTAG DC voltage
Programming voltage
1.5 V DC supply voltage
1.8 V DC supply voltage
2.5 V DC supply voltage
3.3 V DC supply voltage
LVDS differential I/O
LVPECL differential I/O
Analog clean 3.3 V supply to the analog circuitry
Analog 3.3 V supply to ADC
Analog clean 3.3 V supply to the charge pump
Analog 3.3 V supply to sigma-delta DAC
Analog supply to the integrated RC oscillator
External battery supply
Analog supply to the main crystal oscillator
Analog supply to the low power 32 KHz crystal
oscillator
Embedded nonvolatile memory supply
Embedded SRAM supply
Analog 1.5 V supply to the analog circuitry
Analog 1.5 V supply to the ADC
Analog power supply (PLL)
Voltage reference for ADC
Table 2-18 on page
Parameter
2-23. VCCxxxxIOBx should be at the same voltage within a given I/O bank.
1
Programming mode
Operation
R e v i s i o n 6
3
SmartFusion Intelligent Mixed Signal FPGAs
1.425 to 1.575
1.425 to 1.575
1.425 to 1.575
1.425 to 1.575
2.375 to 2.625
1.425 to 1.575
1.425 to 1.575
1.425 to 1.575
Commercial
2.527 to 3.3
3.15 to 3.45
1.425 to 3.6
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
2.7 to 3.63
1.7 to 1.9
2.3 to 2.7
3.0 to 3.6
3.0 to 3.6
0 to +85
0 to 3.6
1.425 to 1.575
1.425 to 1.575
1.425 to 1.575
1.425 to 1.575
2.375 to 2.625
1.425 to 1.575
1.425 to 1.575
1.425 to 1.575
3.15 to 3.45
–40 to +100
1.425 to 3.6
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
3.15 to 3.45
2.527 to 3.3
3.15 to 3.45
3.15 to 3.45
Industrial
2.7 to 3.63
1.7 to 1.9
2.3 to 2.7
3.0 to 3.6
3.0 to 3.6
0 to 3.6
Units
°C
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
2 -3

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