A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 17
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
ACT
Quantity:
36
Company:
Part Number:
A2F200M3F-1FGG256
Manufacturer:
Microsemi SoC
Quantity:
10 000
Company:
Part Number:
A2F200M3F-1FGG256I
Manufacturer:
Microsemi SoC
Quantity:
10 000
- Current page: 17 of 192
- Download datasheet (10Mb)
VCCxxxxIOBx Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCxxxxIOBx ramp-up trip points are about 100 mV higher than ramp-down trip points. This
specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the
following:
PLL Behavior at Brownout Condition
The Microsemi SoC Products Group recommends using monotonic power supplies or voltage regulators
to ensure proper power-up behavior. Power ramp-up should be monotonic at least until VCC and
VCCPLLx exceed brownout activation levels. The VCC activation level is specified as 1.1 V worst-case
(see
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25
V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the "Power-Up/-Down
Behavior of Low Power Flash Devices" chapter of the
information on clock and lock recovery.
Internal Power-Up Activation Sequence
Output buffers, after 200 ns delay from input buffer activation
3. Chip is in the SoC Mode.
•
•
1. Core
2. Input buffers
Figure 2-1 on page 2-6
During programming, I/Os become tristated and weakly pulled up to VCCxxxxIOBx.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
for more details).
R e v i s i o n 6
SmartFusion Intelligent Mixed Signal FPGAs
ProASIC3 FPGA Fabric User’s Guide
2 -5
for
Related parts for A2F200M3F-1FGG256
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
A2F200M3F-FGG256
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
CSP 288/C°/200000 GATES 256KB 80 MHz
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
FPBGA 256/C°/200000 GATES 256KB 80 MHz
Manufacturer:
Actel
Datasheet:
Part Number:
Description:
Manufacturer:
Actel
Datasheet: