ATTINY861-20PU Atmel, ATTINY861-20PU Datasheet - Page 91
ATTINY861-20PU
Manufacturer Part Number
ATTINY861-20PU
Description
Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins
Manufacturer
Atmel
Specifications of ATTINY861-20PU
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
8 KB
Package / Case
PDIP-20
Controller Family/series
AVR Tiny
Core Size
8 Bit
No. Of I/o's
16
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
Ram Size
512 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861-20PU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATTINY861-20PU ES
Manufacturer:
ATMEL
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12.2.5
2588E–AVR–08/10
Definitions
TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR1A, OCR1B, OCR1C and OCR1D can be read
back right after writing the register. The read back values are delayed for the Timer/Counter1
(TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B,
OCF1D and TOV1), because of the input and output synchronization.
The system clock frequency must be lower than half of the PCK frequency, because the syn-
chronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the
PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk
that data or control values are lost.
Figure 12-2. Timer/Counter1 Synchronization Register Block Diagram.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A, B, C or D. However, when using the register or bit
defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1
PCKE
CK
PCK
SYNC
MODE
ASYNC
MODE
IO-registers
OCR1B
OCF1A
OCR1A
OCR1C
OCR1D
TCCR1A
TCCR1B
TCCR1C
TCCR1D
TCNT1
TC1H
OCF1B
OCF1D
TOV1
~1/2 CK Delay
1/2 CK Delay
S
A
Input synchronization
registers
OCR1A_SI
OCR1B_SI
OCR1C_SI
OCR1D_SI
TCCR1A_SI
TCCR1B_SI
TCCR1C_SI
TCCR1D_SI
TCNT1_SI
TC1H_SI
OCF1A_SI
OCF1B_SI
OCF1D_SI
TOV1_SI
1 PCK Delay
1 CK Delay
S
A
8-BIT DATABUS
Timer/Counter1
TCNT1
1 CK Delay
1 PCK Delay
Output synchronization
registers
TCNT1_SO
TC1H_SO
OCF1A_SO
OCF1B_SO
OCF1D_SO
TOV1_SO
1/2 CK Delay
~1 CK Delay
TCNT1
TC1H
OCF1A
OCF1B
OCF1D
TOV1
91
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