ATTINY861-20PU Atmel, ATTINY861-20PU Datasheet - Page 4
![Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins](/photos/16/13/161304/pdip20_sml.jpg)
ATTINY861-20PU
Manufacturer Part Number
ATTINY861-20PU
Description
Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins
Manufacturer
Atmel
Specifications of ATTINY861-20PU
Processor Series
ATTINY8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
2-Wire/SPI/USI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Program Memory Type
Flash
Program Memory Size
8 KB
Package / Case
PDIP-20
Controller Family/series
AVR Tiny
Core Size
8 Bit
No. Of I/o's
16
Eeprom Memory Size
512Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
No. Of Timers
2
Rohs Compliant
Yes
Package
20PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
Ram Size
512 Byte
Operating Temperature
-40 to 85 °C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY861-20PU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATTINY861-20PU ES
Manufacturer:
ATMEL
Quantity:
215
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2. Overview
2.1
4
Block Diagram
ATtiny261/461/861
ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
Figure 2-1.
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
Block Diagram
Timer/Counter0
Generation
PORT B (8)
Watchdog
Watchdog
Oscillator
Oscillator
Circuits /
EEPROM
Timer
Clock
PB[0..7]
USI
Timer/Counter1
POR / BOD &
Supervision
Analog Comp.
PORT A (8)
Power
RESET
Flash
PA[0..7]
3
CPU
debugWIRE
A/D Conv.
PROGRAM
Bandgap
SRAM
Internal
LOGIC
11
RESET
XTAL[1..2]
AVCC
AGND
AREF
2588E–AVR–08/10
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