ATTINY861-20PU Atmel, ATTINY861-20PU Datasheet - Page 147

• Manufacturer Part Number: ATTINY861-20PU
• Description: Microcontrollers (MCU) 8kB Flash 0.512kB EEPROM 16 I/O Pins
• Manufacturer: Atmel

Specifications of ATTINY861-20PU

• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: 2-Wire/SPI/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRMC320
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Package / Case: PDIP-20
• Controller Family/series: AVR Tiny
• Core Size: 8 Bit
• No. Of I/o's: 16
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 512Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• Package: 20PDIP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• Ram Size: 512 Byte
• Operating Temperature: -40 to 85 °C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2588E–AVR–08/10
Figure 15-5. ADC Timing Diagram, Single Conversion
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See
15-6. This assures a fixed delay from the trigger event to the start of conversion. In this mode,
the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 15-6. ADC Timing Diagram, Auto Triggered Conversion
In Free Running mode (see
conversion completes, while ADSC remains high.
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
MUX and REFS
Update
1
2
MUX and REFS
Update
2
3
Figure
Sample & Hold
3
4
Sample &
Hold
4
5
15-7), a new conversion will be started immediately after the
5
6
6
7
One Conversion
7
8
One Conversion
8
9
9
10
Conversion
Complete
10
Conversion
Complete
11
11
12
12
13
13
Sign and MSB of Result
LSB of Result
Sign and MSB of Result
Next Conversion
1
LSB of Result
2
Next Conversion
MUX and REFS
Update
1
Prescaler
Reset
3
Figure
2
147