XRT75R12IB-F Exar Corporation, XRT75R12IB-F Datasheet - Page 80

• Manufacturer Part Number: XRT75R12IB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12IB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: TBGA-420
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 420
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 51.84Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
B
IT
B
7 - 6
N
IT
UMBER
5
7
Reserved
T
ABLE
T
ABLE
PRBS Enable
B
39: XRT75R12 R
Reserved
IT
N
40: C
6
AME
HANNEL
PRBS Enable
Ch_n
B
R/W
IT
T
C
R/W
5
YPE
EGISTER
ONTROL
PRBS Generator and Receiver Enable - Channel_n:
This READ/WRITE bit-field is used to enable or disable the PRBS Generator
and Receiver within a given Channel of the XRT75R12.
If the user enables the PRBS Generator and Receiver, then the following will
happen.
0 - Disables both the PRBS Generator and PRBS Receiver within the corre-
sponding channel.
1 - Enables both the PRBS Generator and PRBS Receiver within the corre-
sponding channel.
N
(n = [0:11] &
OTES
1. The PRBS Generator (which resides within the Transmit Section of
2. The PRBS Receiver (which resides within the Receive Section of the
MAP
R
RLB_n
B
1. To check and monitor PRBS Bit Errors, DR (Dual Rail) mode will be
2. If the user enables the PRBS Generator and PRBS Receiver, the
3. The system must provide an accurate and stable data-rate clock to
R/W
EGISTER
the Channel) will begin to generate an unframed, 2^15-1 PRBS
Pattern (for DS3 and STS-1 applications) and an unframed, 2^23-1
PRBS Pattern (for E3 applications).
Channel) will now be enabled and will begin to search the incoming
data for the above-mentioned PRBS patterns.
:
IT
4
over-ridden and Single Rail mode forced for the duration of this
mode. This will configure the RNEG/LCV_n output pin to function
as a PRBS Error Indicator. All errors will be flagged on this pin.
The errors will also be accumulated in the 16 bit Error counter for
the channel.
Channel will ignore the data that is being accepted from the
System-side Equipment (via the TxPOS_n and TxNEG_n input
pins) and will overwrite this outbound data with the PRBS Pattern.
the TxClk_n pin during this operation.
SHOWING
77
M
- C
= 0-5 & 8-D)
HANNEL
LLB_n
B
C
R/W
IT
HANNEL
3
n A
C
D
DDRESS
ONTROL
ESCRIPTION
E3_n
B
R/W
IT
2
L
R
OCATION
EGISTERS
STS-1/DS3_n
B
R/W
= 0
IT
1
(CC_n)
XM
6
SR/DR_n
REV. 1.0.4
B
R/W
IT
0