XRT75R12IB-F Exar Corporation, XRT75R12IB-F Datasheet - Page 64

• Manufacturer Part Number: XRT75R12IB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12IB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Package / Case: TBGA-420
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 3.135V To 3.465V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: BGA
• No. Of Pins: 420
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 51.84Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT75R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
N
Reserved
UMBER
7, 6
B
B
5
4
3
2
1
0
IT
IT
7
T
ABLE
Channel 5 Interrupt Status
Channel 4 Interrupt Status
Channel 3 Interrupt Status
Channel 2 Interrupt Status
Channel 1 Interrupt Status
Channel 0 Interrupt Status
24: C
Reserved
B
IT
HANNEL
Reserved
6
N
AME
Interrupt Sta-
L
Channel 5
EVEL
B
R/O
tus
IT
5
I
NTERRUPT
Interrupt Sta-
T
R/O
Channel 4
YPE
B
R/O
S
tus
IT
TATUS
4
Channel n Interrupt Status Bit:
This READ-ONLY bit-field indicates whether the XRT75R12 has a
pending Channel n-related interrupt that is awaiting service. The
first six channels are serviced through this location and the other
six at address 0xE1. These two registers are used by the Host to
identify the source channel of an active interrupt.
0 - Indicates that there is NO Channel n-related Interrupt awaiting
service.
1 - Indicates that there is at least one Channel n-related Interrupt
awaiting service. In this case, the user's Interrupt Service routine
should be written such that the Microprocessor will now proceed
to read out the contents of the Source Level Interrupt Status Reg-
ister - Channel n (Address Locations = 0xn2) to determine the
exact source of the interrupt request.
N
OTE
61
R
: Once this bit-field is set to "1", it will not be cleared back to
Interrupt Sta-
EGISTER
Channel 3
"0" until the user has read out the contents of the Source-
Level Interrupt Status Register bit, that corresponds to the
interrupt request channel.
B
R/O
tus
IT
3
- CR97 (A
Interrupt Sta-
Channel 2
B
R/O
D
tus
IT
DDRESS
ESCRIPTION
2
L
Interrupt Sta-
Channel 1
OCATION
B
R/O
tus
IT
1
= 0
X
Interrupt Sta-
61)
Channel 0
REV. 1.0.4
B
R/O
tus
IT
0