MCIMX513DJM8CR2 Freescale Semiconductor, MCIMX513DJM8CR2 Datasheet - Page 92

• Manufacturer Part Number: MCIMX513DJM8CR2
• Description: IC MPU I.MX51 529MABGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX513DJM8CR2

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 800MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Electrical Characteristics
The maximal accuracy of UP/DOWN edge of controls is
92
1
2
IP5o
IP13o Offset of VSYNC
IP8o
IP9o
DISP_CLK_PERIOD—number of DI_CLK per one Tdicp. Resolution 1/16 of DI_CLK
DI_CLK_PERIOD—relation of between programing clock frequency and current system clock frequency
Display interface clock period average value.
ID
Display interface clock period immediate value.
DI’s counter can define offset, period and UP/DOWN characteristic of output signal according to programed parameters of the
counter. Same of parameters in the table are not defined by DI’s registers directly (by name), but can be generated by
corresponding DI’s counter. The SCREEN_WIDTH is an input value for DI’s HSYNC generation counter. The distance
between HSYNCs is a SCREEN_WIDTH.
Offset of IPP_DISP_CLK
Offset of HSYNC
Offset of DRDY
Table 80. Synchronous Display Interface Timing Characteristics (Pixel Level) (continued)
Tdicp
Parameter
=
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
⎧
⎪
⎪
⎨
⎪
⎪
⎩
T diclk floor
T diclk
⎛
⎝
×
DISP_CLK_PERIOD
------------------------------------------------------ -
DI_CLK_PERIOD
DISP_CLK_PERIOD
------------------------------------------------------ -
Symbol
DI_CLK_PERIOD
Todicp
Todrdy
Tohs
Tovs
Tdicp
Accuracy
=
T diclk
DISP_CLK_OFFSET
VSYNC_OFFSET
HSYNC_OFFSET
DRDY_OFFSET
,
=
×
×
×
×
×
(
Value
0.5
Tdiclk
Tdiclk
Tdiclk
Tdiclk
+
DISP_CLK_PERIOD
------------------------------------------------------ -
DI_CLK_PERIOD
0.5
×
T diclk
±
0.5
⎞
⎠
) 0.75ns
,
±
DISP_CLK_OFFSET— offset of
IPP_DISP_CLK edges from local start
point, in DI_CLK
(0.5 DI_CLK Resolution)
Defined by DISP_CLK counter
VSYNC_OFFSET—offset of Vsync edges
from a local start point, when a Vsync
should be active, in DI_CLK
(0.5 DI_CLK Resolution).The
VSYNC_OFFSET should be built by
suitable DI’s counter.
HSYNC_OFFSET—offset of Hsync edges
from a local start point, when a Hsync
should be active, in DI_CLK
(0.5 DI_CLK Resolution).The
HSYNC_OFFSET should be built by
suitable DI’s counter.
DRDY_OFFSET— offset of DRDY edges
from a suitable local start point, when a
corresponding data has been set on the
bus, in DI_CLK
(0.5 DI_CLK Resolution)
The DRDY_OFFSET should be built by
suitable DI’s counter.
for fractional
for integer
DISP_CLK_PERIOD
------------------------------------------------------ -
DISP_CLK_PERIOD
------------------------------------------------------ -
DI_CLK_PERIOD
Description
×
DI_CLK_PERIOD
×
2
2
Freescale Semiconductor
×
×
2
2
Unit
ns
ns
ns
ns