MCIMX513DJM8CR2 Freescale Semiconductor, MCIMX513DJM8CR2 Datasheet - Page 125

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MCIMX513DJM8CR2

Manufacturer Part Number
MCIMX513DJM8CR2
Description
IC MPU I.MX51 529MABGA
Manufacturer
Freescale Semiconductor
Series
i.MX51r
Datasheet

Specifications of MCIMX513DJM8CR2

Core Processor
ARM Cortex-A8
Core Size
32-Bit
Speed
800MHz
Connectivity
1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
128
Program Memory Type
ROMless
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.8 V ~ 1.15 V
Oscillator Type
External
Operating Temperature
-20°C ~ 85°C
Package / Case
529-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
4.7.12.1 Reset Sequence
4.7.12.1.1
The sequence of reset for this kind of SIM Cards is as follows (see
4.7.12.1.2
The sequence of reset for this kind of card is as follows (see
Freescale Semiconductor
SIMx_DATAy_RX_TX
SIMx_SVENy
SIMx_CLKy
After power up, the clock signal is enabled on SIMx_CLKy(time T0)
After 200 clock cycles, RX must be high.
The card must send a response on RX acknowledging the reset between 400 and 40000 clock
cycles after T0.
After power-up, the clock signal is enabled on SIMx_CLKy (time T0)
After 200 clock cycles, SIMx_DATAy_RX_TX must be high.
SIMx_RSTy must remain Low for at least 40000 clock cycles after T0 (no response is to be
received on RX during those 40000 clock cycles)
SIMx_RSTy is set High (time T1)
SIMx_RSTy must remain High for at least 40000 clock cycles after T1 and a response must be
received on SIMx_DATAy_RX_TX between 400 and 40000 clock cycles after T1.
Cards with internal reset
Cards with Active Low Reset
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
T0
1
Figure 84. Internal-Reset Card Reset Sequence
2
response
400 clock cycles <
Figure
Figure
85):
84):
1
2
Electrical Characteristics
< 200 clock cycles
< 40000 clock cycles
125

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