FSAM10SH60A Fairchild Semiconductor, FSAM10SH60A Datasheet - Page 13

• Manufacturer Part Number: FSAM10SH60A
• Description: SMART POWER MODULE 10A SPM32-AA
• Manufacturer: Fairchild Semiconductor
• Series: SPM™r
• Type: IGBTr

Specifications of FSAM10SH60A

• Configuration: 3 Phase
• Current: 10A
• Voltage: 600V
• Voltage - Isolation: 2500Vrms
• Package / Case: SPM32AA
• Collector- Emitter Voltage Vceo Max: 600 V
• Collector-emitter Saturation Voltage: 2.5 V
• Continuous Collector Current At 25 C: 10 A
• Power Dissipation: 43 W
• Mounting Style: SMD/SMT
• Transistor Polarity: N Channel
• Dc Collector Current: 10A
• Collector Emitter Voltage Vces: 2.5V
• Power Dissipation Pd: 43W
• Collector Emitter Voltage V(br)ceo: 600V
• Operating Temperature Range: -20°C To +125°C
• Rohs Compliant: Yes
• Input Voltage: 253V
• Output Current: 20A
• Supply Voltage Range: 13.5V To 16.5V
• No. Of Pins: 32
• Filter Terminals: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FSAM10SH60A_NL; FSAM10SH60A_NL

©2003 Fairchild Semiconductor Corporation
Note:
1) It would be recommended that by-pass capacitors for the gating input signals, IN
2) The logic input is compatible with standard CMOS or LSTTL outputs.
3) R
Note:
and on the both sides of CPU and SPM for the fault output signal, V
to each of SPM pins.
It would be recommended that the bootstrap diode, D
PL
C
PL
CPU
/R
470uF
PH
C
PH
/R
15V-Line
PF
C
PF
Fig. 14. Recommended Bootstrap Operation Circuit and Parameters
coupling at each SPM input is recommended in order to prevent input/output signals’ oscillation and it should be as close as possible
These Values depend on PW M C ontrol Algorithm
20
Ω
1nF
Fig. 13. Recommended CPU I/O Interface Circuit
0.1uF
100
100
100
D
22uF
B S
Ω
Ω
Ω
BS
, has soft and fast recovery characteristics.
4.7k
R
C
1nF
P F
P F
0.1uF
Ω
FO
, as close as possible.
0.47nF
C
2k
R
P L
One-Leg Diagram of SPM
(UL)
P L
Ω
, IN
5V-Line
IN
IN
COM
COM
Vcc
Vcc
(VL)
, IN
OUT
HO
VB
VS
(WL)
4.7k
1.2nF
R
C
P H
P H
, IN
Ω
(UH)
, IN
(VH)
and IN
CO M
IN
IN
V
FO
(UH)
(WH)
(UL)
P
N
,
,
should be placed on the SPM pins
IN
IN
Inverter
Output
(VH)
(VL)
SPM
,
,
IN
IN
(WH)
(WL)
Rev. E, August 2003