ATA5278-PKQI Atmel, ATA5278-PKQI Datasheet
ATA5278-PKQI
Specifications of ATA5278-PKQI
Related parts for ATA5278-PKQI
ATA5278-PKQI Summary of contents
Page 1
... Power-down Mode for Minimum Power Consumption 1. Description The ATA5278 device is an integrated BCDMOS antenna driver IC dedicated as a transmitter for Passive Entry/Go (PEG) car applications and for other hands-free access control applications. It includes the full functionality of generating a magnetic LF field in conjunction with an antenna coil to transmit data to a receiver in a key fob, card or transponder ...
Page 2
... Boost 5V converter regulator control ATA5278 HS driver LS driver Driver control logic Current and zero crossing sensing DGND SCANE TEST PGND1 1 PGND2 2 PGND3 3 VDS ATA5278 4 DRV1 5 CBOOST 6 QSC MODACTIVE OSCI OSCO VIF NRES CLKO S_CS Oscillator S_CLK Voltage interface S_DI S_DO Control and ...
Page 3
... Data output of serial interface 24 VDD Internal 5 V stabilizing capacitor connection 25 VBATT Battery supply 26 VL1 Coil connection for the boost converter low-side switch 27 VL2 Coil connection for the boost converter low-side switch 28 VL3 Coil connection for the boost converter low-side switch 4832D–RKE–12/07 ATA5278 3 ...
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... Power-down Mode The ATA5278 should be kept in power-down mode as long as the LF channel is not used, because not only is the current consumption minimal, but the internal logic is also reset. The antenna driver stage is in high impedance mode. To power-up the chip, the chip-select line (S_CS) has to be activated for an appropriate time ...
Page 5
... Figure 3-2. Note that if command 4 is omitted and only the chip-select line is disabled, the ATA5278 stays operational (i.e., the oscillator keeps running, an eventually running LF data modulation is not interrupted). Here, only the SPI itself is disabled and the serial bus can be used for other devices connected to it. 4832D– ...
Page 6
... In case the microcontroller is not able to communicate properly with the ATA5278 or any other disturbance has occurred, it can trigger a reset (like a power-on-reset, POR) in the chip by pull- ing the NRES pin to ground, which will bring the logic back to the startup state, i.e., all configurations are at default and the power-down mode. ...
Page 7
... All digital I/O pins, including the reset input pin NRES, are passed through the internal voltage interface before they reach their concerning blocks. This interface prevents possible compensa- tion currents, as the control logic of the ATA5278 is supplied by the internal 5V regulator capable of handling I/O voltages between 3.15V and 5.5V, determined by the voltage applied to the VIF pin ...
Page 8
... SPI The control interface of the ATA5278 consists of an eight-bit synchronous SPI. It has a clock input (S_CLK) which supports frequencies MHz, a chip select line (S_CS) which enables the interface, a serial data input (S_DI) and a serial data output (S_DO). The output pin tristate type, which will be set to high-impedance state as soon as the chip-select line is dis- abled ...
Page 9
... S_DO Z 3.7 SPI Commands The microcontroller can access the following functions of the ATA5278 via the SPI: • Read from/write to configuration register 1 • Read from/write to configuration register 2 • Read from the status register • Write LF transmission data to the buffer and start the transmission • ...
Page 10
... Table 3-1. SPI Commands No. I/O MSB IC3 IC3 HB7 HB6 HB5 ATA5278 LSB RTS RTS RTS RTS RTS 0 IC2 IC1 IC0 RTS IC2 IC1 IC0 RTS BR1 BR0 RTS BR1 BR0 RTS RTS RTS 0 HB4 HB3 HB2 HB1 HB0 Description Check status of IC ...
Page 11
... Table 3-1 on page 10 ATA5278. Each command consists of one or more data words which the controller has to trans- fer to the SPI of the ATA5278. An SPI data word is always eight bits in width and has to be transferred starting with the least significant bit (LSB). The following list contains detailed information on every command of the chip. ...
Page 12
... The status register of the ATA5278 can be read out with command 9. As soon as the internal diagnosis stage detects a fault stored in the status register until a fault reset command is given or a power-on-reset occurs. Note that the power stages of the chip are disabled as long as a power stage fault (i ...
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... LF Data Modulation The LF modulator stage of the ATA5278 is fed with data from the LF data buffer started after a successfully received SPI command 11. Two half bits are loaded at a time and brought sequentially to the driver control logic, starting with the half bit labeled lower in applied for half the period time selected by the LF baud rate selector ...
Page 14
... Figure 3-10. LF Data Modulation with PSK Half bit X values Driver control input Driver control signal Resulting antenna signal MODACTIVE pin Start of modulation ATA5278 Bitlength t Bitlength Figure 3-9 has a length of four logical bits and therefore eight half bits the period of one logical bit, which is defined by the selected data baud rate in ...
Page 15
... If data rates above 2 kbauds are demanded or the PSK modulation mode is selected, the use of an external antenna current loop switch is mandatory. This switch has to be controlled in a defined way which is supported by the ATA5278. For further details on this topic, please refer to the section 3 ...
Page 16
... The gate of the external transistor is driven by the QSC pin of the ATA5278. The signal provided here is suited to drive standard MOSFETs (i.e., no logic-level FETs). During power-down mode or a fault shutdown, the external transistor is switched off. Otherwise, this would lead to a con- ducting state as long as no data modulation takes place. For further information on this pin, please refer to the table “ ...
Page 17
... Current Regulation A main feature of the ATA5278 is its ability to generate a stabilized magnetic field with a con- nected LC antenna, mainly independent of the battery voltage and the frequency mismatch between the driver output frequency and the antenna resonance frequency. ...
Page 18
... Boost Converter The ATA5278 provides the supply current for its driver stage by means of a Switch Mode Power Supply (SMPS) in boost configuration. A low-side switch that charges the inductor, and the therefore needed control circuitry is integrated. The other necessary components such as the inductor, the free-wheeling diode and the charging capacitor have to be applied externally ...
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... I /2.604 1 maximum I /2.353 0 maximum I /2.132 1 maximum I /1.984 0 maximum I /1.825 1 maximum I /1.709 0 maximum I /1.57 1 maximum I /1.456 0 maximum I /1.361 1 maximum I /1.256 0 maximum I /1.163 1 maximum I /1.081 0 maximum ( maximum 1. Default ATA5278 provides a list of the current settings for all 16 IC1 IC2 IC3 /64) OSC P/P ratio 1 ...
Page 20
... As the low-side antenna driver transistor and the QSC transistor are also both active in standby mode, faults concerning these devices are also monitored then. Only during power-down, no fault monitoring is active. Figure 3-15 on page 21 ATA5278 20 illustrates the fault shutdown timing sequence. 4832D–RKE–12/07 ...
Page 21
... PCB boundaries. The clock signal is directly derived from the clock source connected to the OSCI/OSCO pins of the ATA5278 and is available as long as the ATA5278 is not in power-down mode. The fre- quency can be selected with the prescaler (PS) bit in configuration register 2, which is 0 for the full-clock rate (f 4832D– ...
Page 22
... MODACTIVE Output Pin The MODACTIVE pin of the ATA5278 can be used to directly control a timer/counter stage of the microcontroller. The signal indicates LF data modulation activity. In conjunction with suited timers and counting stages in the microcontroller, it enables the software to precisely know the progress of the LF data transmission. For further details, see 3-10 on page 14 3 ...
Page 23
... The parameters given in to the needs of the internal circuitry and the application. • The clock supply for the ATA5278 can be either an active clock source connected to the OSCI pin passive device like a crystal or a ceramic resonator. When using a crystal, the prolonged oscillation build-up time (typically ms) needs to be considered ...
Page 24
... Figure 3-17. Power Dissipation versus Supply Voltage The static thermal resistance of the chip, soldered onto a PCB can hardly be lowered beneath 30 K/W. Hence, a static operation of ATA5278 is not possible in all cases. But as most applica- tions require only a temporary LF field, the dynamic thermal effects (i.e., the thermal capacitances) are important parameters that must be taken into account ...
Page 25
... Ta = 105 ˚ C 0.1 0 1.5 2.5 3.5 Power Dissipation ( K/W for the case-to-copper resistance R th,jc th,pcba and the thermal capacitance of the package are fixed values, but th,jc ATA5278 ˚ 4.5 5.5 6.5 7.5 and 20 K/W for the th,cpcb 50 mm 0.05 mm, 25 ...
Page 26
... Thermal resistance junction-ambient (1) (QFN28) Note reach this value, special measures on the PCB have to be taken 6. Operating Range Parameters Power supply range (1) Operating temperature range Note: 1. For details, please refer to the section ATA5278 26 Symbol V BATT V INP V IND P tot EMI 1.5 (all pins vs. each other) ESD 4 (pins ...
Page 27
... V OUT OUTH 23 12, 16 OUT OUTL S_CS S_DO ODIS VIF 13 RESHLD V 0 NRES VIF NRES ATA5278 Min. Typ. Max 4.7 5.5 0.1 1.5 3.5 8 0.5 1.2 2.2 0.5 0.5 1.05 3.15 5.5 0.6 V VIF 0.3 V VIF 0,03 0, VIF VIF 15 60 – ...
Page 28
... Integrator lower voltage 4.7 limiting current (source) Integrator current 4.8 de-pendency from antenna current Integrator current for 4.9 antenna current step 1 *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5278 28 Test Conditions Pin Symbol V = 12V VDS V = 18V CBOOST ...
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... Current step 14 VSHUNT,p SMPL14 860 mV Current step 15 VSHUNT,p SMPL15 925 mV Current step 16 VSHUNT,p SMPL16 1000 mV ATA5278 Min. Typ. Max. –0.93 +1.24 –1.038 +1.39 –1.152 +1.53 –1.275 +1.6 –1.41 +1.66 –1.51 +1.72 –1.44 +1.84 –1.52 +2.0 –1.67 +2.15 –1.76 +2.36 –1.87 +2.55 – ...
Page 30
... Maximum output voltage High-side output voltage 6.2 under load Low-side output voltage 6.3 under load Switch-on signal rise 6.4 time *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA5278 30 Test Conditions Pin Symbol V = 18V VL1-3 –40°C T 26-28 ...
Page 31
... OSCO OSCI 0.8V OSCO V < 0.5 OSCI 19 t LOW,max V VDD Power-down mode OSCI, OSCI OSCO t deb ATA5278 Min. Typ. Max 5 OSCI 4/f OSCI 4/f OSCI 100 100 100 100 100 8 140 400 2.0 3.7 1.1 1.8 –3.7 –2.0 –2.0 –1.2 660 ...
Page 32
... Type means 100% tested 100% correlation tested Characterized on samples Design parameter 8. Soldering Recommendations Parameters Maximum heating rate Peak temperature in preheat zone Duration of time above melting point of solder Peak reflow temperature Maximum cooling rate ATA5278 32 Test Conditions Pin Symbol DRV1 short-circuit 5 t deb,min ...
Page 33
... Ordering Information Extended Type Number ATA5278-PKQI 10. Package Information Package: QFN Exposed pad 4.3 x 4.3 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances ± 0. Drawing-No.: 6.543-5098.01-4 Issue: 1; 28.02.03 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document ...
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