MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 59

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
10.5.5.4 CRCPresetLSB register
10.5.5.5 CRCPresetMSB register
10.5.5.6 PreSet25 register
Table 94.
[1]
LSB of the preset value for the CRC register.
Table 95.
Table 96.
MSB of the preset value for the CRC register.
Table 97.
Table 98.
These values must not be changed.
Table 99.
Bit
1
0
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Bit
7 to 0 CRCPresetMSB[7:0]
Bit
Symbol
Access
With ISO/IEC 14443 A, this bit must be set to logic 1.
Symbol
Symbol
ParityOdd
ParityEn
Symbol
CRCPresetLSB[7:0]
ChannelRedundancy bit descriptions
CRCPresetLSB register (address: 23h) reset value: 0101 0011b, 63h bit allocation
CRCPresetLSB register bit descriptions
CRCPresetMSB register (address: 24h) reset value: 0101 0011b, 63h bit
allocation
CRCPresetMSB bit descriptions
PreSet25 register (address: 25h) reset value: 0000 0000b, 00h bit allocation
7
7
All information provided in this document is subject to legal disclaimers.
7
1
Value
0
1
0
Rev. 3.3 — 15 March 2010
6
6
6
Function
odd parity is generated or expected
even parity is generated or expected
a parity bit is inserted in the transmitted data stream after each byte
and expected in the received data stream after each byte (MIFARE,
ISO/IEC 14443 A)
no parity bit is inserted or expected
048033
Description
defines the starting value for CRC calculation. This value is
loaded into the CRC at the beginning of transmission, reception
and the CalcCRC command (if the CRC calculation is enabled)
Remark: This register is not relevant if CRC8 is set to logic 1.
Description
defines the start value for CRC calculation. This value is loaded
into the CRC at the beginning of transmission, reception and
the CalcCRC command (if CRC calculation is enabled).
5
5
5
CRCPresetMSB[7:0]
CRCPresetLSB[7:0]
Highly Integrated ISO/IEC 14443 A Reader IC
4
4
4
00000000
…continued
R/W
R/W
R/W
3
3
3
[1]
2
2
2
MFRC500
© NXP B.V. 2010. All rights reserved.
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0
0
0