MFRC50001T/0FE,112 NXP Semiconductors, MFRC50001T/0FE,112 Datasheet - Page 45

• Manufacturer Part Number: MFRC50001T/0FE,112
• Description: IC MIFARE READER 32-SOIC
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC50001T/0FE,112

• Rf Type: Read Only
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B, ISO15693
• Package / Case: 32-SOIC (0.300", 7.50mm Width)
• Product: RFID Readers
• Operating Temperature Range: - 25 C to + 85 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2222-5; 935268039112; MFRC500; MFRC51T0FED

NXP Semiconductors
MFRC500_33
Product data sheet
PUBLIC
10.5.1.4 PrimaryStatus register
Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 39.
Table 40.
Bit
Symbol
Access
Bit
7
6 to 4 ModemState[2:0]
3
2
1
0
Symbol
0
IRq
Err
HiAlert
LoAlert
PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation
PrimaryStatus register bit descriptions
All information provided in this document is subject to legal disclaimers.
R
7
0
Rev. 3.3 — 15 March 2010
Value Status
-
000
001
010
011
100
101
110
111
-
1
1
1
6
ModemState[2:0]
048033
Idle
TxSOF
TxData
TxEOF
GoToRx1
GoToRx2
PrepareRx
AwaitingRx
Receiving
R
5
Highly Integrated ISO/IEC 14443 A Reader IC
4
Description
reserved
shows the state of the transmitter and receiver
state machines:
shows any interrupt source requesting attention
based on the InterruptEn register flag settings
any error flag in the ErrorFlag register is set
the alert level for the number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
otherwise value = logic 0
Example:
the alert level for number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
value = logic 0
Example:
HiAlert
LoAlert
neither the transmitter or receiver are operating;
neither of them are started or have input data
transmit start of frame pattern
transmit data from the FIFO buffer (or
redundancy CRC check bits)
transmit End Of Frame (EOF) pattern
intermediate state 1; receiver starts
intermediate state 2; receiver finishes
waiting until the RxWait register time period
expires
receiver activated; waiting for an input signal on
pin RX
receiving data
FIFOLength = 60, WaterLevel = 4 then
HiAlert = logic 1
FIFOLength = 59, WaterLevel = 4 then
HiAlert = logic 0
FIFOLength = 4, WaterLevel = 4 then
LoAlert = logic 1
FIFOLength = 5, WaterLevel = 4 then
LoAlert = logic 0
IRq
R
3
=
=
(
FIFOLength WaterLevel
64 FIFOLength
–
Err
R
2
≤
MFRC500
HiAlert
) WaterLevel
© NXP B.V. 2010. All rights reserved.
R
≤
1
otherwise
LoAlert
45 of 110
R
0