AT86RF401U-XI Atmel, AT86RF401U-XI Datasheet - Page 17

IC MICRO TX RF W/AVR 20-TSSOP

AT86RF401U-XI

Manufacturer Part Number
AT86RF401U-XI
Description
IC MICRO TX RF W/AVR 20-TSSOP
Manufacturer
Atmel
Datasheet

Specifications of AT86RF401U-XI

Frequency
264MHz ~ 456MHz
Applications
Garage Opener, RKE, Telemetry
Modulation Or Protocol
ASK, OOK
Data Rate - Maximum
10 kbps
Power - Output
6dBm
Current - Transmitting
23.2mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
2KB Flash, 128 Byte EEPROM, 128Byte SRAM
Voltage - Supply
2 V ~ 5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
AT86RF401U
1424F–RKE–12/03
Figure 6. AVR Core Architecture
The AVR uses a Harvard architecture concept, with separate memories and buses for
program and data. The program memory is executed with a two-stage pipeline. While
one instruction is being executed, the next instruction is prefetched from the program
memory. This concept enables instructions to be executed in every clock cycle. The pro-
gram memory is in-system, reprogrammable Flash memory.
With the jump and call instructions, the whole 1K word address space is directly
accessed. Most AVR instructions have a single 16-bit word format. Every program
memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is
stored on the stack. The stack is effectively allocated in the general data SRAM, and
consequently the stack size is only limited by the total SRAM size and the usage of the
SRAM. All user programs must initialize the SP in the reset routine (before subroutines
or interrupts are executed). The 7-bit stack pointer SP is read/write accessible in the I/O
space.
The 128-byte data SRAM can be easily accessed through the five different addressing
modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
Control Lines
Instruction
Instruction
Program
1K x 16
Register
Decoder
Memory
Program
Counter
and Control
EEPROM
Registers
128 x 8
128 x 8
Purpose
General
SRAM
Data Bus 8-bit
Status
32 x 8
Data
ALU
AT86RF401
Battery Detector
Brown-out/Low
Programmable
Clock Divider
Transmitter
Watchdog
Bit Timer
I/O Lines
SPI Unit
Timer
RF
6
17

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