AT86RF401U-XI Atmel, AT86RF401U-XI Datasheet
AT86RF401U-XI
Specifications of AT86RF401U-XI
Related parts for AT86RF401U-XI
AT86RF401U-XI Summary of contents
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... Wireless PC Peripherals (Keyboard, Mouse) • Telemetry (Tire Pressure, Utility Meter, Asset Tracking) Description The Atmel AT86RF401 Smart RF Microtransmitter is a highly integrated, low-cost RF transmitter, combined with an AVR RISC microcontroller. It requires only a crystal, a single LiMnO coin cell (CR2032 or similar), three capacitors, an inductor and a tuned- ...
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... The RF signal output is placed dif- ferentially on a tuned-loop antenna, which may be realized as a counterspread copper trace on a PCB. The AT86RF401 is fabricated in Atmel’s 0.6 µm Mixed Signal CMOS + EEPROM pro- cess, enabling true system-level integration (SLI). Figure 2. 20-lead TSSOP ...
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Figure 3. Sample Circuit EXTERNAL LOOP FILTER (OPTIONAL SDI RESET SDO SCLK SPI Programming Interface Table 1. Recommended Parts List Value Part Number (Common) B1 3. 100 pF C3 Antenna Dependent C4 C5 ...
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Table 2. Pin Descriptions – 20-lead TSSOP Symbol Pin 1 ANTB 1 V VCO V DD LOOPFIL VCO VDD AT86RF401 4 Description 20 Differential Antenna Output ...
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Table 2. Pin Descriptions – 20-lead TSSOP (Continued RESETB Data nable I/O0 (SDI) 7 Data Enable Data Enable I/O1 (SDO) 8 Data Enable Data Enable I/O2 (SCK) 9 Data Enable 10 XTAL/CLK 10 11 1424F–RKE–12/03 ...
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Table 2. Pin Descriptions – 20-lead TSSOP (Continued) 10 XTALB 11 11 Data Enable IO3 12 Data Enable Data Enable IO4 13 Data Enable Data Enable IO5 14 Data Enable DGND 15 AGND 16 DVDD 17 AT86RF401 ...
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Table 2. Pin Descriptions – 20-lead TSSOP (Continued) AVDD 18 N ANT 20 1424F–RKE–12/03 Analog Voltage Supply No Connect – Float Pin 20 Differential Antenna Output 10 mA AT86RF401 7 ...
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Absolute Maximum Ratings* Antenna Voltage (Pins 1, 20) Operating Temperature Storage Temperature (without bias) Voltage on V with respect to ground ............................. 6.0V DD Voltage on Pins 2–19 (TSSOP 20) Table 3. DC Characteristics V = 3.3V 13.125 ...
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Table 4. Analog/RF Specs V = 3.3V 13.125 MHz XTAL AVR Symbol Parameter RF Amplifier I Power Amp Output Current PA P Power Control Range CTLRANGE P Power Control Resolution CTLRES Crystal Oscillator f Oscillation Frequency ...
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Bandgap Reference Brown-out Protection/Low Battery Detection Brown-out Protection Low Battery Detection AT86RF401 10 period. A number of registers are available to adjust the performance of the lock detec- tor. These include lock delay and unlock delay timers as well as ...
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... I/O3 pin. This enables the AT86RF401 to be used to decode the signal detected by an external receiver chip. For additional information on how to implement the bit timer, see AT86RF401 Bit Timer Application Note, available at www.atmel.com. Bit coding is done by the AVR before data is sent to the bit timer. Bit timing is controlled by the count value in the Bit Timer Count (BTCNT) register and the two most significant bits in the Bit Timer Control Register (BTCR) ...
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Watchdog Timer Reset and Interrupt Handling Address Labels Code $000 jmp $002 jmp $004 jmp $006 MAIN: <instr> … … … Reset Sources AT86RF401 12 When enabling the watchdog timer, the status of the watchdog time is unknown. The user ...
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Interrupt Response Time Memory Programming Program Memory Lock Bits In-system Flash and EEPROM SPI Interface 1424F–RKE–12/03 During power-on reset and watchdog reset, all I/O registers are set to their initial values, and the program starts execution from address $000. Note: ...
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... SDO the end of the programming session, RESETB must be set high to commence normal operation. All Atmel microcontrollers have a three-byte signature code that identifies the device. For the AT86RF401, the signature bytes are: • 0x000: 0x1E (indicates manufactured by Atmel) • ...
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Data EEPROM Access from the AVR Table 7. AT86RF401 Serial Programming Instruction Set Instruction Byte 1 Programming 1010 1100 Enable Chip Erase 1010 1100 Read Program 0010 H000 Memory Write Program 0100 H000 Memory Read 1010 0000 EEPROM Memory Write ...
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Figure 5. Serial Programming Waveforms SERIAL DATA INPUT (SDI) SERIAL DATA OUTPUT (SDO) SERIAL CLOCK INPUT (SCK) Note: This device includes an integrated 128-byte EEPROM, which is accessed by three registers located in the I/O memory space. These are the ...
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Figure 6. AVR Core Architecture Program Counter Program Memory Instruction Register Instruction Decoder Control Lines The AVR uses a Harvard architecture concept, with separate memories and buses for program and data. The program memory is executed ...
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AT86RF401 18 A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All interrupts have a separate interrupt vector in the interrupt vector table at the beginning ...
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General-purpose Register File 1424F–RKE–12/03 Figure 8 shows the structure of the 32 general-purpose working registers in the CPU. Figure 8. AVR CPU General-purpose Working Registers 7 All the register operating instructions in the instruction set have direct and single cycle ...
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The X, Y and Z Registers Figure 9. The X, Y and Z Registers 15 X Register 70 R27 ($1B Register 70 R29 ($1D Register 70 R30 ($1F) Arithmetic Logic Unit (ALU) In-system Self- programmable Flash ...
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SRAM Data Memory Program and Data Addressing Modes 1424F–RKE–12/03 Figure 10 shows how the AT86RF401 SRAM memory is organized. Figure 10. SRAM Organization Register File ... R29 R30 R31 I/O Registers $00 $01 $02 ... $3D $3E ...
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Register Direct, Single Register Rd Register Direct, Two Registers Rd and Rr I/O Direct AT86RF401 22 Figure 11. Direct Single Register Addressing The operand is contained in register d (Rd). Figure 12. Direct Register Addressing, Two Registers Operands are contained ...
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Data Direct Data Indirect with Displacement Data Indirect 1424F–RKE–12/03 Figure 14. Direct Data Addressing LSBs 15 A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or ...
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Data Indirect with Pre-decrement Data Indirect with Post-increment Constant Addressing Using the LPM Instruction AT86RF401 24 Figure 17. Data Indirect Addressing with Pre-decrement REGISTER The register is decremented before the ...
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Indirect Program Addressing, IJMP and ICALL Relative Program Addressing, RJMP and RCALL 1424F–RKE–12/03 Figure 20. Indirect Program Memory Addressing Program execution continues at address contained by the Z register (i.e., the PC is loaded with the contents of the Z ...
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EEPROM Data Memory Memory Access Times and Instruction Execution Timing AT86RF401 26 The AT86RF401 contains 128 bytes of data EEPROM memory organized as a sep- arate data space in which single bytes can be read and written. The ...
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The internal data SRAM access is performed in two System Clock cycles as described in Figure 24. Figure 24. On-chip Data SRAM Access Cycles T1 System Clock Ø Address Prev. Address Data Write Data Read All I/Os and peripherals ...
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I/O Memory The I/O space definition of the AT86RF401 is shown in Table 8 below. Table 8. AT86RF401 I/O Space Definitions Address Hex $3F $3E $3D $35 $34 $33 $32 $31 $30 $22 $21 $20 $1E $1D $1C $17 $16 ...
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I/O and Control Registers Transmitter Control Register Descriptions Lock Detector Configuration Register 1 – LOCKDET1 Bit 7 $10 – Read/Write R/W Initial Value 0 1424F–RKE–12/03 The AT86RF401 I/Os and peripherals are placed in the I/O space. The various I/O loca- ...
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Transmit Control Register – TX_CNTL Bit 7 $12 – Read/Write R/W Initial Value 0 Power Attenuation Control Register – PWR_ATTEN Bit 7 $14 – Read/Write R/W Initial Value 0 AT86RF401 – TXE TXK R/W R/W R/W ...
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VCO Tuning Register 6 – VCOTUNE Bit 7 $16 VCOVDET[1] VCOVDET[0] Read/Write R Initial Value * 1424F–RKE–12/03 • Bits[5:3]: PCC, Power Control (coarse) Attenuates the output power steps. Table 10. Coarse Power Control Definition PCC[5:3] 000 001 ...
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AT86RF401 32 Table 12. VCO Tuning Capacitor Definition VCOTUNE[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 ...
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Lock Detector Configuration Register 2 – LOCKDET2 Bit 7 $17 EUD LAT Read/Write R/W R/W Initial Value 0 1424F–RKE–12/03 • Bits[7:6]: VCO Voltage Detector The VCO Voltage Detector circuit monitors the level of the VCO control voltage. This cir- cuit, ...
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AT86RF401 34 • Bit[5:3]: ULC[2:0] The unlock count (ULC) bits count a certain number of reference clocks, after which the unlock detect circuit looks for a number of cycle slips determined by CS[1:0] before making the loc detect signal go ...
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EEPROM Control Register Descriptions Data EEPROM Control Register – DEECR Bit 7 $1C – Read/Write R/W Initial Value 0 0 1424F–RKE–12/ – – – R/W R/W R • Bits[7:4] R eserved . These bits ...
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Data EEPROM Data Register – DEEDR Bit 7 $1D ED7 Read/Write R/W Initial Value 0 0 Data EEPROM Address Register – DEEAR Bit 7 $1E – Read/Write R/W Initial Value 0 0 AT86RF401 ED6 ED5 ED4 ...
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Bit Timer Register Descriptions Bit Timer Count Register – BTCNT Bit 7 $20 C7 Read/Write R/W Initial Value 0 Bit Timer Control Register – BTCR Bit 7 $21 C9 Read/Write R/W Initial Value 0 1424F–RKE–12/ ...
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Watchdog Timer Control Register – WDTCR Bit 7 6 $22 – – Read/Write R R Initial Value 0 0 AT86RF401 38 • Bit[2]: Flag2 In transmit mode, this flag indicates the Transmit Done condition that occurs when the buffer is ...
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I/O Enable Register – IO_ENAB Bit 7 $30 – Read/Write R/W Initial Value 0 1424F–RKE–12/03 When the WDE is set (“1”), the Watchdog Timer is enabled, and if the WDE is cleared (“0”), the Watchdog Timer function is disabled. WDE ...
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I/O Data Out Register – IO_DATOUT Bit 7 $31 – Read/Write R Initial Value 0 I/O Data In Register – IO_DATIN Bit 7 $32 – Read/Write R/W Initial Value 0 AVR Configuration Register – AVR_CONFIG Bit 7 $33 – Read/Write ...
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I/O5 txkey Normal Mode (RESETB = 1) (Output) txkey SPI Mode (RESETB = 0) (Output) Notes: 1. IO_ENAB register is NOT used for SPI pins SPI mode, the I/O registers may be directly accessed via the SPI interface. ...
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Button Detect Register – B_DET Bit 7 $34 – Read/Write R Initial Value 0 Battery Low Configuration Register – BL_CONFIG Bit 7 $35 BL Read/Write R Initial Value 0 AT86RF401 42 code execution at the reset location. This bit is ...
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Table 21. Low Battery Detection Threshold Formulas (V V Falling DD 3.887 V REF VDD = ---------------------------------------------------------- - 0.887 -------------- - 1 BL[5: REF BL[5:0] 71 3.887 ------------ - = – 1424F–RKE–12/03 is approximately 0.7 ...
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The Stack Pointer – SP Bit 15 14 $3E – $3D SP7 SP6 7 Read/Write R R R/W R/W Initial Value 0 0 The Status Register – SREG Bit 7 $3F I Read/Write R/W Initial Value 0 AT86RF401 44 The ...
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Table 22. Instruction Set Mnemonics Operands Description Arithmetic and Logic Instructions ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract Two Registers SUBI Rd, K ...
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Table 22. Instruction Set (Continued) Mnemonics Operands Description CLR Rd Clear Register SER Rd Set Register Branch Instructions RJMP k Relative Jump IJMP Indirect Jump to (Z) JMP k Direct Jump RCALL k Relative Subroutine Call ICALL Indirect Call to ...
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Table 22. Instruction Set (Continued) Mnemonics Operands Description BRVC k Branch if Overflow Flag Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled Data Transfer Instructions MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy ...
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Table 22. Instruction Set (Continued) Mnemonics Operands Description OUT P, Rr Out Port PUSH Rr Push Register on Stack POP Rd Pop Register from Stack Bit and Bit-test Instructions SBI P, b Set Bit in I/O Register CBI P, b ...
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... Ordering Information RF Output Ordering Code 315 MHz AT86RF401U 434 MHz AT86RF401E 264 to 456 MHz AT86RF401X 1424F–RKE–12/03 Package Application 20T North American 20T European 20T All Applications AT86RF401 Temperature Operating Range ...
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Package Drawing 20A2 – TSSO Top View A Side View Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional information. 2. Dimension D does not include ...
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Data Sheet Change Log Changes from Rev. 1424E-RKE-03/03 to Rev. 1424F-RKE-9/03 1424F–RKE–12/03 Please note that the page numbers referenced below apply to this document. • Updated text in Low Battery Detection section on page 10. • Table 3, in Low ...
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