SI4022-A1-FT Silicon Laboratories Inc, SI4022-A1-FT Datasheet - Page 9

• Manufacturer Part Number: SI4022-A1-FT
• Description: IC TX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Band FSK Transmitterr

Specifications of SI4022-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Applications: ISM
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 115.2kbps
• Power - Output: 6dBm
• Current - Transmitting: 24mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 434 MHz to 915 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Supply Current: 24 mA
• Supply Voltage (max): 3.8 V
• Supply Voltage (min): 2.2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1623-5

CONTROL INTERFACE
Commands to the transmitters are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on
pin SCK whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. The number of bits
sent is an integer multiple of 8 (except for the Transmitter FIFO Write Command). All commands consist of a command code,
followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no
influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command
registers.
Timing Specification
Timing Diagram
Symbol
t
t
t
t
t
t
t
t
CH
CL
SS
SH
SHI
DS
DH
OD
nSEL
SCK
SDI
SDO
t
SS
t
Parameter
Clock high time
Clock low time
Select setup time (nSEL falling edge to SCK rising edge)
Select hold time (SCK falling edge to nSEL rising edge)
Select high time
Data setup time (SDI transition to SCK rising edge)
Data hold time (SCK rising edge to SDI transition)
Data delay time
DS
BIT15
BIT15
t
t
DH
CH
t
CL
BIT14
BIT14
t
OD
BIT13
BIT13
BIT8
BIT8
BIT7
BIT7
BIT1
BIT1
Minimum value [ns]
BIT0
BIT0
t
SH
25
25
10
10
25
10
5
5
t
SHI
Si4022
9