SI4022-A1-FT Silicon Laboratories Inc, SI4022-A1-FT Datasheet - Page 12

• Manufacturer Part Number: SI4022-A1-FT
• Description: IC TX FSK 915MHZ 3.8V 16-TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: ISM Band FSK Transmitterr

Specifications of SI4022-A1-FT

• Package / Case: 16-TSSOP
• Frequency: 868MHz, 915MHz
• Applications: ISM
• Modulation Or Protocol: FSK
• Data Rate - Maximum: 115.2kbps
• Power - Output: 6dBm
• Current - Transmitting: 24mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Voltage - Supply: 2.2 V ~ 3.8 V
• Operating Temperature: -40°C ~ 85°C
• Operating Frequency: 434 MHz to 915 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Supply Current: 24 mA
• Supply Voltage (max): 3.8 V
• Supply Voltage (min): 2.2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Memory Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1623-5

N o t e
N o t e
FIFO Setting Command
Bit 7 <fe>:
Bit 5-0 <f5 : f0>:
Transmitter FIFO register write
Data Transmit Sequence Through the FSK Pin
It is possible to transmit data without the FIFO by using the FSK input pin. In that case the power amplifier should be enabled first with
the Power Management Comand.
N o t e
N o t e
N o t e :
bit
• If the crystal oscillator was formerly switched off (ex=0), the internal oscillator needs t
• If the synthesizer was formerly switched off (es=0), the internal PLL needs t
the type of quartz crystal used.
internal locking process is finished.
15
1
nSEL
SCK
SDI
FSK
nSEL
SDI
SCK
14
1
Enables the 64 bit transmit FIFO. Resetting this bit clears the contents of the FIFO.
FIFO IT level. The FIFO generates IT when number of the remaining data bits in the FIFO reaches this level.
13
0
Internal operations
0
ex, es, etr = 1
P o w e r M a n a g e m e n t c o m m a n d
12
0
1
C 0 h
11
1
2
synthesizer / PLL /
Xtal osc staus
instruction
PA status
10
instruction
3
1
d o n ' t c a r e
4
9
1
5
8
0
3 8 h
6
fe
7
7
6
0
t
sx *
0
f5
5
1
sp
f4
4
t
sp *
startup time. Valid data can be transmitted only when the
2
f3
3
synthesizer on, PLL locked, PA ready to transmit
sx
filling up FIFO
3
xtal osc. stable
time, to switch on. The actual value depends on
N data bits
f2
2
4
f1
T X D A T A
1
NOTE:
* See page 5 for the timing values
5
f0
0
N-2
N-1
CE00h
POR
Si4022
12