SI4022-A1-FT Silicon Laboratories Inc, SI4022-A1-FT Datasheet

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SI4022-A1-FT

Manufacturer Part Number
SI4022-A1-FT
Description
IC TX FSK 915MHZ 3.8V 16-TSSOP
Manufacturer
Silicon Laboratories Inc
Type
ISM Band FSK Transmitterr
Datasheet

Specifications of SI4022-A1-FT

Package / Case
16-TSSOP
Frequency
868MHz, 915MHz
Applications
ISM
Modulation Or Protocol
FSK
Data Rate - Maximum
115.2kbps
Power - Output
6dBm
Current - Transmitting
24mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Voltage - Supply
2.2 V ~ 3.8 V
Operating Temperature
-40°C ~ 85°C
Operating Frequency
434 MHz to 915 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V, 3.3 V
Supply Current
24 mA
Supply Voltage (max)
3.8 V
Supply Voltage (min)
2.2 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Memory Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1623-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SI4022-A1-FT
Manufacturer:
SILICON
Quantity:
470
Part Number:
SI4022-A1-FT
Manufacturer:
SILICONLABS/芯科
Quantity:
20 000
Company:
Part Number:
SI4022-A1-FT
Quantity:
500
Si4022 Universal ISM Band
FSK Transmitter
DESCRIPTION
Integration’s Si4022 is a single chip, low power, multi-channel FSK
transmitter designed for use in applications requiring FCC or ETSI
conformance for unlicensed use in the bands at 868 and 915 MHz. Used in
conjunction with Integration’s FSK receivers, it is a flexible, low cost, and
highly integrated solution that does not require production alignments. All
required RF functions are integrated. Only an external crystal and bypass
filtering is needed for operation.
The transmitter has a completely integrated PLL for easy RF design, and its
rapid settling time allows for fast frequency-hopping, bypassing multipath
fading and interference to achieve robust wireless links. The PLL’s high
resolution allows the usage of multiple channels in any of the bands. In
addition, highly stable and accurate FSK modulation is accomplished by
direct closed-loop modulation with bit rates up to 115.2 kbps.
The integrated power amplifier of the transmitter has an open-collector
differential output and can directly drive a loop antenna with programmable
output level, no additional matching network is required. An automatic
antenna tuning circuit is built in to avoid both costly trimming procedures
and de-tuning due to the “hand effect”.
For battery-operated applications the device supports various power saving
modes with wake-up interrupt generation options based on a low battery
voltage detector and a sleep timer. Several additional features ease system
design. Power-on reset and clock signals are provided to the microcontroller.
An on-chip baud rate generator and a data FIFO are available. The transmitter
is programmed and controlled via an SPI compatible interface.
IA4222-DS rev 1.1r 0308
VREFO
VSS_A
VDD_B
VSS_D
VDD
XTL
15
11
14
9
8
7
OSCILLATOR
CRYSTAL
BATTERY
WAKE -UP
DETECT
TIMER
LOW
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
TRESHOLD
LOAD CAP
LOW BAT
TIMEOUT
PERIOD
CLOCK
SYNTHESIZER
CONTROLLER
nRES
10
FREQUENCY
LEVEL
13
12
16
6
5
4
1
2
3
RF02
RF01
CLK
nIRQ
SDO
SDI
SCK
nSEL
FSK
FEATURES
• Fully integrated (low BOM, easy design-in)
• No alignment required in production
• Fast settling, programmable, high-resolution PLL
• Fast frequency hopping capability
• Stable and accurate FSK modulation with
• Programmable PLL loop bandwidth
• Direct loop antenna drive
• Automatic antenna tuning circuit
• Programmable output power level
• SPI bus for interfacing with microcontroller
• Clock and reset signals for microcontroller
• 64 bit TX data FIFO
• Integrated programmable crystal load capacitor
• Standard 10 MHz crystal reference
• Power-saving modes
• Multiple event handling options for wake-up
• Wake-up timer
• Low battery detection
• 2.2 to 3.8 V supply voltage
• Low power consumption
• Low standby current (typ. 0.3 μA)
TYPICAL APPLICATIONS
• Remote control
• Home security and alarm
• Wireless keyboard/mouse and other PC peripherals
• Toy control
• Remote keyless entry
• Tire pressure monitoring
• Telemetry
• Personal/patient data logging
• Remote automatic meter reading
See www.silabs.com/integration for any applicable
programmable deviation
activation
errata. See back page for ordering information.
This document refers to Si4022-IC Rev A0.
VREFO
VSS_D
nSEL
nIRQ
SCK
SDO
CLK
SDI
PIN ASSIGNMENT
PIN ASSIGNMENT
PIN ASSIGNMENT
PIN ASSIGNMENT
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
Si4022
www.silabs.com/integration
15
14
13
12
11
10
16
9
FSK
VDD
VSS_B
RF02
RF01
VSS_A
nRES
XTL / REF
1

Related parts for SI4022-A1-FT

SI4022-A1-FT Summary of contents

Page 1

... Si4022 Universal ISM Band FSK Transmitter DESCRIPTION Integration’s Si4022 is a single chip, low power, multi-channel FSK transmitter designed for use in applications requiring FCC or ETSI conformance for unlicensed use in the bands at 868 and 915 MHz. Used in conjunction with Integration’s FSK receivers flexible, low cost, and highly integrated solution that does not require production alignments ...

Page 2

... DETAILED FEATURE-LEVEL DESCRIPTION The Si4022 FSK transmitter is designed to cover the unlicensed frequency bands at 868, and 915 MHz. The device facilitates compliance with FCC and ETSI requirements. PLL The programmable PLL synthesizer determines the operating frequency, while preserving accuracy based on the on-chip crystal-controlled reference oscillator. The PLL’ ...

Page 3

... Reset output (active low) S Negative supply voltage (analog differential signal output (open collector differential signal output (open collector) S Negative supply voltage (bulk) S Positive supply voltage DI Data input for asynchronous modulation Si4022 FSK VDD VSS_B RF02 RF01 VSS_A nRES XTL / REF Description 3 ...

Page 4

... MHz band out max all blocks disabled crystal oscillator is ON programmable in 0.1 V steps 2.0 larger glithches on the V dd generate a POR even above the threshold V POR for proper POR generation 0.1 Si4022 Max Units 6 +0 1000 V o 125 C o 260 ...

Page 5

... Frequency error < 1kHz after 1 MHz step Initial calibration after power-up with running crystal oscillator Programmable in 0.5 pF steps, 8.5 tolerance +/- 10% After V has reached 90 final value Crystal ESR < 100 Ω Calibrated every 40 seconds 0.995 (Note 3) 1 Si4022 Typ Max Units 0.3 µA 1 µA 0 ...

Page 6

... Note 4: Note 4: The maximum FSK bitrate and the output phase noise are dependent on the PLL settings (with the Extended Features Command). Note 5: Note 5: Note 5: Note 5: Optimal antenna / admittance / inductance for the Si4022 Note 5: Note 6: Note 6: Note 6: Note 6: Note 6: With selective resonant antennas (see: Application Notes available from http://www.silabs.com/integration). ...

Page 7

... Spot Freq 1 MHz Spot Freq 1 MHz Spot Freq 1 MHz At 915 MHz L 10:34:57 May 5, 2005 Atten VBW 10 kHz Sweep 40.74 ms (2001 pts) Si4022 1.00000 MHz -101.95 dBc/Hz 10 MHz Value -101.95 dBc/Hz -107.05 dBc/Hz -109.98 dBc/Hz Mkr1 915.0020 MHz -14.09 dBm Span 2 MHz 7 ...

Page 8

... At 868 MHz with 180 kHz Deviation at 9.6 kbps 11:14:40 May 5, 2005 L Atten 10 dB VBW 10 kHz Sweep 40.74 ms (2001 pts) Antenna Tuning Characteristics 750–970 MHz Si4022 Span 2 MHz 8 ...

Page 9

... Data setup time (SDI transition to SCK rising edge Data hold time (SCK rising edge to SDI transition Data delay time OD Timing Diagram t SS nSEL SCK SDI BIT15 BIT14 SDO BIT15 BIT14 t OD BIT13 BIT8 BIT7 BIT13 BIT8 BIT7 Si4022 Minimum value [ns SHI t SH BIT1 BIT0 BIT1 BIT0 9 ...

Page 10

... The resulting output frequency can be calculated as out 0 where the channel center frequency (see the 0 next command the three bit binary number <m2 : m0> SIGN = (ms) XOR (FSK input POR 9082h Crystal Load x1 x0 Capacitance [ 10.0 … 15 16.0 – (- (20 kHz) SIGN Si4022 10 ...

Page 11

... Transmitter FIFO Write Command Bit With this command, the controller can write databits to the transmitter FIFO. Bit (fe) must be set in the FIFO Setting Command f10 The constant C is determined by the selected band as: Band [MHz] 868 915 POR Si4022 POR AD57h POR etr C002h etr ...

Page 12

... PA status N-2 N filling up FIFO N data bits xtal osc. stable sp * synthesizer on, PLL locked, PA ready to transmit NOTE: * See page 5 for the timing values time, to switch on. The actual value depends on sx startup time. Valid data can be transmitted only when the POR CE00h Si4022 12 ...

Page 13

... These bits can be used for further fine adjustment of the wake-up timer. The explanation of the bits can be found above elfc Clock Output Frequency [MHz wake- m13 m12 m11 m10 POR C813h POR C213h of the detector 1.25 1.66 2 2.5 3. POR E196h ms R POR m9 m8 C300h Si4022 13 ...

Page 14

... Wake-up timer overflow POR Power-on reset Status Register Read Sequence nSEL SCK SDI SDO FFIT FFEM FFOV LBD exlp ctls 0 dcal bw1 bw0 PLL bandwidth kHz kHz kHz 1 1 120 kHz WK-UP POR POR bw1 bw0 dsfi ewi B0CAh POR status out Si4022 14 ...

Page 15

... Bit dcal in the Extended Features Command (page 14) controls the automatic calibration feature reset power-on and the automatic calibration is enabled. This is necessary to compensate for process tolerances. After one calibration cycle further (re)calibration can be disabled by setting this bit slow < 0 slow x Si4022 clock periods are not to scale T fast + T from the slow fast ) half cycle. The ...

Page 16

... In order to get accurate values the AFC has to be disabled during the read by clearing the "en" bit in the AFC Control Command (bit 0). VDD L3 to RFP RFN C2 Si4022 50 Ohm load GND GND 16 ...

Page 17

... CRYSTAL SELECTION GUIDELINES The crystal oscillator of the Si4022 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to minimize the external component count. The internal load capacitance value is programmable from 8 0.5 pF steps. With appropriate PCB layout, the total load capacitance value can variety of crystal types can be used. ...

Page 18

... Data packet structure Data packet structure Data packet structure Data packet structure An example data packet structure using theSi4022 –Si4022 pair for data transmission. This packet structure is an example of how to use the high efficiency FIFO mode at the receiver side Prea mble The first 3 bytes compose a 24 bit length ‘01’ pattern to let enough time for the clock recovery of the receiver to lock. The next two bytes compose a 16 bit synchron pattern which is essential for the receiver’ ...

Page 19

... PACKAGE INFORMATION 16-pin TSSOP Si4022 19 ...

Page 20

... ORDERING INFORMATION Si4022 Universal ISM Band FSK Transmitter DESCRIPTION Si4022 16-pin TSSOP die Demo Boards and Development Kits DESCRIPTION ISM Chipset Development Kit Related Resources DESCRIPTION Antenna Selection Guide Antenna Development Guide IA4322 Universal ISM Band FSK Receiver Note: Volume orders must include chip revision to be accepted. ...

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