SI1013-A-GM Silicon Laboratories Inc, SI1013-A-GM Datasheet - Page 60

• Manufacturer Part Number: SI1013-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1013-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1870-5

Table 4.4. Reset Electrical Characteristics
V
Si1010/1/2/3/4/5
60
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
VDD/DC+ Monitor Thresh-
old (V
VBAT Ramp Time for
Power On
VBAT Monitor Threshold
(V
Missing Clock Detector
Timeout
Minimum System Clock w/
Missing Clock Detector
Enabled
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V
V
Current
DD
DD
DD
POR
= 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Monitor Turn-on Time
Monitor Supply 
RST
)
Parameter
)
Initial Power-On (VBAT Rising)
Early Warning
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
Time from last system clock rising edge
System clock frequency which triggers
Delay between release of any reset
a missing clock detector timeout
(all power modes except Sleep)
execution at location 0x0000
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
VBAT Ramp from 0–0.9 V
V
V
V
V
source and code
to reset initiation
DD
DD
DD
DD
Early Warning
Reset Trigger
I
OL
Conditions
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 1.4 mA,
Rev. 1.0
V
0.7 x V
DD
Min
100
1.8
1.7
0.9
0.7
15
—
—
—
—
—
—
—
—
—
—
—
—
– 0.6
DD
1.85
1.75
0.75
0.95
Typ
525
300
1.0
0.8
—
—
—
—
20
10
—
10
—
—
4
2
0.3 x V
1000
Max
0.6
0.6
1.9
1.8
1.1
0.9
35
10
—
—
—
—
—
—
—
—
—
3
DD
Units
kHz
µA
ms
µA
µs
µs
µs
ns
V
V
V
V
V
V
V