SI1013-A-GM Silicon Laboratories Inc, SI1013-A-GM Datasheet - Page 179

• Manufacturer Part Number: SI1013-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1013-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1870-5

Si1010/1/2/3/4/5
16.8. DC-DC Converter Behavior in Sleep Mode
When the Si1014/5 devices are placed in Sleep mode, the dc-dc converter is disabled, and the
VDD_MCU/DC+ output is internally connected to VBAT by default. This behavior ensures that the GPIO
pins are powered from a low-impedance source during sleep mode. If the GPIO pins are not used as
inputs or outputs during sleep mode, then the VDD_MCU/DC+ output can be made to float during Sleep
mode by setting the VDDSLP bit in the DC0CF register to 1.
Setting this bit can provide power savings in two ways. First, if the sleep interval is relatively short and the
VDD_MCU/DC+ load current (include leakage currents) is negligible, then the capacitor on
VDD_MCU/DC+ will maintain the output voltage near the programmed value, which means that the
VDD_MCU/DC+ capacitor will not need to be recharged upon every wake up event. The second power
advantage is that internal or external low-power circuits that require more than 1.8 V can continue to func-
tion during Sleep mode without operating the dc-dc converter, powered by the energy stored in the 1 µF
output decoupling capacitor. For example, the Si1014/5 comparators require about 0.4 µA when operating
in their lowest power mode. If the dc-dc converter output were increased to 3.3 V just before putting the
device into Sleep mode, then the comparator could be powered for more than 3 seconds before the output
voltage dropped to 1.8 V. In this example, the overall energy consumption would be much lower than if the
dc-dc converter were kept running to power the comparator.
If the load current on VDD_MCU/DC+ is high enough to discharge the VDD_MCU/DC+ capacitance to a
voltage lower than VBAT during the sleep interval, an internal diode will prevent VDD_MCU/DC+ from
dropping more than a few hundred millivolts below VBAT. There may be some additional leakage current
from VBAT to ground when the VDD_MCU/DC+ level falls below VBAT, but this leakage current should be
small compared to the current from VDD_MCU/DC+.
The amount of time that it takes for a device configured in one-cell mode to wake up from Sleep mode
depends on a number of factors, including the dc-dc converter clock speed, the settings of the SWSEL,
ILIMIT, and LPEN bits, the battery internal resistance, the load current, and the difference between the
VBAT voltage level and the programmed output voltage. The wake up time can be as short as 2 µs, though
it is more commonly in the range of 5 to 10 µs, and it can exceed 50 µs under extreme conditions.
See Section “14. Power Management” on page 157 for more information about sleep mode.
16.9. Bypass Mode
During normal operation, if the dc-dc converter input voltage exceeds the programmed output voltage, the
converter will stop switching and the Diode Bypass switch will remain in the “on” state. The output voltage
will be equal to the input voltage minus any resistive loss in the switch and all of the converter’s analog cir-
cuits will remain biased. The bypass feature automatically shuts off the dc-dc converter when the input
voltage is greater than the programmed output voltage by 150 mV. In bypass, the Diode Bypass switch and
dc-dc converter bias currents are disabled except for the voltage comparison circuitry (~ 3 µA, depending
on the configuration settings in the DC0MD register). If the input voltage drops within 50 mV of the pro-
grammed output value, then the dc-dc converter automatically starts operating in the normal state. There is
100 mV voltage hysteresis built in the bypass comparator to enhance stability.
The bypass mode increases system operating time in systems which have a minimum operating voltage
higher than the battery end of life voltage. For instance, if an external chip requires a minimum supply volt-
age of 2.7 V and a lithium coin cell battery is used as power source (end-of-life voltage is approximately
2 V), then the C8051F912/902’s dc-dc converter could be configured for an output voltage of 2.7 V with
bypass mode enabled. The dc-dc converter would be bypassed when the battery was fresh, but as soon
as the battery voltage dropped below 2.75 V, the dc-dc converter would turn on to ensure that the external
chip was provided with a minimum of 2.7 V for the remainder of the battery life.
Rev. 1.0
179