SI1013-A-GM Silicon Laboratories Inc, SI1013-A-GM Datasheet - Page 270

IC TXRX MCU + EZRADIOPRO

SI1013-A-GM

Manufacturer Part Number
SI1013-A-GM
Description
IC TXRX MCU + EZRADIOPRO
Manufacturer
Silicon Laboratories Inc
Datasheets

Specifications of SI1013-A-GM

Package / Case
42-QFN
Frequency
240MHz ~ 960MHz
Data Rate - Maximum
256kbps
Modulation Or Protocol
FSK, GFSK, OOK
Applications
General Purpose
Power - Output
13dBm
Sensitivity
-121dBm
Voltage - Supply
1.8 V ~ 3.6 V
Current - Receiving
18.5mA
Current - Transmitting
30mA
Data Interface
PCB, Surface Mount
Memory Size
8kB Flash, 768B RAM
Antenna Connector
PCB, Surface Mount
Number Of Receivers
1
Number Of Transmitters
1
Wireless Frequency
240 MHz to 960 MHz
Interface Type
UART, SMBus, SPI, PCA
Output Power
13 dBm
Operating Supply Voltage
0.9 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Supply Current
4 mA
Minimum Operating Temperature
- 40 C
Modulation
FSK, GFSK, OOK
Protocol Supported
C2, SMBus
Core
8051
Program Memory Type
Flash
Program Memory Size
8 KB
Data Ram Size
768 B
Supply Current (max)
4 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Operating Temperature
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1870-5
Si1010/1/2/3/4/5
23.5.8. Crystal Oscillator
The transceiver includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than
600 µs when a suitable parallel resonant crystal is used. The design is differential with the required crystal
load capacitance integrated on-chip to minimize the number of external components. By default, all that is
required off-chip is the 30 MHz crystal.
The crystal load capacitance can be digitally programmed to accommodate crystals with various load
capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load
capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load
Capacitance". The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps
(97fF/step). The xtalshift bit provides a coarse shift in frequency but is not binary with xlc[6:0].
The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing
the on-chip temperature sensor and suitable control software, the temperature dependency of the crystal
can be canceled.
The typical value of the total on-chip capacitance Cint can be calculated as follows:
Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift
Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by
the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If
the maximum value of Cint (16.3 pF) is not sufficient, an external capacitor can be added for exact tuning.
Additional information on calculating Cext and crystal selection guidelines is provided in “AN417: Si4x3x
Family Crystal Oscillator.”
If AFC is disabled then the synthesizer frequency may be further adjusted by programming the Frequency
Offset field fo[9:0]in "Register 73h. Frequency Offset 1" and "Register 74h. Frequency Offset 2", as dis-
cussed in “Frequency Control” on page 255.
The crystal oscillator frequency is divided down internally and may be output to the microcontroller through
one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for
the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration
are discussed further in “Output Clock” on page 280.
The transceiver may also be driven with an external 30 MHz clock signal through the XOUT pin. When
driving with an external reference or using a TCXO, the XTAL load capacitance register should be set to 0.
Add R/W Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR
Def.
09
R/W
Crystal Oscillator Load
xtalshift
xlc[6]
xlc[5]
xlc[4]
xlc[3]
xlc[2]
xlc[1]
xlc[0]
7Fh
Capacitance
23.5.9. Regulators
There are a total of six regulators integrated onto the transceiver. With the exception of the digital regulator,
all regulators are designed to operate with only internal decoupling. The digital regulator requires an exter-
nal 1 µ F decoupling capacitor. All regulators are designed to operate with an input supply voltage from
+1.8 to +3.6 V. The output stage of the of PA is not connected internally to a regulator and is connected
directly to the battery voltage.
A supply voltage should only be connected to the VDD pins. No voltage should be forced on the digital reg-
ulator output.
270
Rev. 1.0

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