SI1013-A-GM Silicon Laboratories Inc, SI1013-A-GM Datasheet - Page 105

• Manufacturer Part Number: SI1013-A-GM
• Description: IC TXRX MCU + EZRADIOPRO
• Manufacturer: Silicon Laboratories Inc

Specifications of SI1013-A-GM

• Package / Case: 42-QFN
• Frequency: 240MHz ~ 960MHz
• Data Rate - Maximum: 256kbps
• Modulation Or Protocol: FSK, GFSK, OOK
• Applications: General Purpose
• Power - Output: 13dBm
• Sensitivity: -121dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Current - Receiving: 18.5mA
• Current - Transmitting: 30mA
• Data Interface: PCB, Surface Mount
• Memory Size: 8kB Flash, 768B RAM
• Antenna Connector: PCB, Surface Mount
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 240 MHz to 960 MHz
• Interface Type: UART, SMBus, SPI, PCA
• Output Power: 13 dBm
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 4 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK, GFSK, OOK
• Protocol Supported: C2, SMBus
• Core: 8051
• Program Memory Type: Flash
• Program Memory Size: 8 KB
• Data Ram Size: 768 B
• Supply Current (max): 4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1870-5

7.2. Comparator Outputs
When a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the
voltage at the negative input. When disabled, the comparator output is a logic 0. The comparator output is
synchronized with the system clock as shown in Figure 7.2. The synchronous “latched” output (CP0, CP1)
can be polled in software (CPnOUT bit), used as an interrupt source, or routed to a Port pin (configured for
digital I/O) through the Crossbar.
The asynchronous “raw” comparator output (CP0A, CP1A) is used by the low power mode wake-up logic
and reset decision logic. See the Power Options chapter and the Reset Sources chapter for more details
on how the asynchronous comparator outputs are used to make wake-up and reset decisions. The asyn-
chronous comparator output can also be routed directly to a Port pin through the Crossbar, and is available
for use outside the device even if the system clock is stopped.
When using a Comparator as an interrupt source, Comparator interrupts can be generated on rising-edge
and/or falling-edge comparator output transitions. Two independent interrupt flags (CPnRIF and CPnFIF)
allow software to determine which edge caused the Comparator interrupt. The comparator rising-edge and
falling-edge interrupt flags are set by hardware when a corresponding edge is detected regardless of the
interrupt enable state. Once set, these bits remain set until cleared by software.
The rising-edge and falling-edge interrupts can be individually enabled using the CPnRIE and CPnFIE
interrupt enable bits in the CPTnMD register. In order for the CPnRIF and/or CPnFIF interrupt flags to gen-
erate an interrupt request to the CPU, the Comparator must be enabled as an interrupt source and global
interrupts must be enabled. See the Interrupt Handler chapter for additional information.
Analog Input Multiplexer
Px.x
Px.x
Px.x
Px.x
Figure 7.2. Comparator 1 Functional Block Diagram
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1OUT
CP1RIF
CP1EN
CP1FIF
CP1 +
CP1 -
+
-
Rev. 1.0
VDD
GND
Decision
Reset
CPT0MD
Tree
(ASYNCHRONOUS)
(SYNCHRONIZER)
D
SET
CLR
Q
Q
D
SET
CLR
Q
Q
Si1010/1/2/3/4/5
Rising-edge
CP1
Crossbar
Interrupt
Logic
Falling-edge
Interrupt
CP1
CP1A
CP1
CP1
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