MRF89XA-I/MQ Microchip Technology, MRF89XA-I/MQ Datasheet - Page 7

• Manufacturer Part Number: MRF89XA-I/MQ
• Description: TXRX ISM SUB-GHZ ULP 32QFN
• Manufacturer: Microchip Technology

Specifications of MRF89XA-I/MQ

• Package / Case: 32-WFQFN Exposed Pad
• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 863 MHz to 870 MHz, 902 MHz to 928 MHz, 950 MHz to 960 MHz
• Interface Type: SPI
• Noise Figure: - 112 dBc
• Output Power: - 8.5 dBm, + 12.5 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Data Rate: 256 Kbps
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.0
Microchip Technology's MRF89XA is a fully integrated,
half-duplex, sub-GHz transceiver. This low-power,
single chip RF FSK and OOK baseband transceiver
supports:
• Super Heterodyne Architecture
• Multi-Channel, Multi-Band Synthesizer with
• Power Amplifier (PA)
• Low Noise Amplifier (LNA)
• I/Q Two Stage Down Converter Mixers
• I/Q Demodulator, FSK/OOK
• Baseband Filters and Amplifiers
The simplified functional block diagram of MRF89XA is
shown in Figure 1-1.
The MRF89XA is a good choice for low-cost,
high-volume, low data rate (<256 kbps), two-way short
range wireless applications. This is a single chip FSK
and OOK transceiver capable of operation in the
863-870 MHz and 902-928 MHz license-free ISM
frequency bands, as well as the 950-960 MHz
frequency band.
The low-cost MRF89XA is optimized for very low-power
consumption (3 mA in Receiver mode). It incorporates a
baseband modem with data rates up to 200 kb/s in FSK
and 32 kb/s in OOK. Data handling features include a
64-byte FIFO, packet handling, automatic CRC genera-
tion and data whitening. The device also supports
Manchester coding techniques. Its highly integrated
architecture allows for minimum external component
count while still maintaining design flexibility. All major
RF communication parameters are programmable and
most of them may be dynamically set.
The MRF89XA complies with European (ETSI EN
300-220 V2.1.1) and North American (FCC Part 15.247
and 15.249) regulatory standards, and therefore, can
be used for all applications looking for FCC, IC, or ETSI
certification in the ISM band and licensed bands also.
The MRF89XA supports a stable sensitivity and
linearity characteristics for a wide supply range and is
internally regulated. The frequency synthesizer of the
MRF89XA is a fully integrated integer-N type PLL. The
PLL circuit requires only five external components for
the PLL loop filter and the VCO tank circuit. The PLL
and low phase noise provides for excellent adjacent
channel rejection capability, Bit Error Rate (BER) and
larger communication coverage along with higher
output power.
 2010 Microchip Technology Inc.
Phase Lock Loop (PLL) for easy RF Design
OVERVIEW
Advance Information
The crystal oscillator provided on the MRF89XA device
provides the reference clock for the PLL. In order to
minimize the total system cost, a communication link in
most of the applications can be created using a
low-cost, generic 12.8 MHz crystal, a bypass filter and
an affordable microcontroller. The MRF89XA provides
a clock signal for the microcontroller and avoids the
need for a second crystal on the circuit board. The
transceiver can be interfaced with many popular
Microchip PIC
rupt (IRO), PLL lock and clock out. The interface
between the microcontroller and MRF89XA is shown in
Figure 1-1.
The MRF89XA supports the following digital data
processing features:
• PLL and I/Q VCO Configuration
• Receiver Signal Strength Indicator
• Sync Word Recognition
• Packet Handler
• Interrupt and Flags
• Different Operating Modes (Continuous, Buffer
• Data Filtering/Whitening/Encoding
• Baseband Power Amplifier
• TX/RX Data Buffer
The role is to interface the data to/from the
modulator/demodulator and the microcontroller access
points (SPI, IRQ and DATA pins). It also controls all the
Configuration registers. The receiver's Baseband Band-
width (BBBW) can be programmed to accommodate
various deviations and data rates requirements.
The high-resolution PLL allows:
• The usage of multiple channels in any of the
• The rapid settling time allows for faster frequency
An optional Bit Synchronizer (BitSync) is provided, to
supply a synchronous clock and data stream to a
companion microcontroller in Continuous mode, or to
fill the FIFO with glitch-free data in Buffered mode. The
transceiver is integrated with different power-saving
modes and an internal wake-up time to keep track of
the activities, which reduces the overall current con-
sumption and extends the battery life. The small size
and low-power consumption of the MRF89XA makes it
ideal for various short range radio applications.
and Packet)
bands
hopping, bypassing multi-path fading and
interference to achieve robust wireless links
®
microcontrollers via a 4-wire SPI, inter-
MRF89XA
DS70622A-page 7