MRF89XA-I/MQ Microchip Technology, MRF89XA-I/MQ Datasheet - Page 13

• Manufacturer Part Number: MRF89XA-I/MQ
• Description: TXRX ISM SUB-GHZ ULP 32QFN
• Manufacturer: Microchip Technology

Specifications of MRF89XA-I/MQ

• Package / Case: 32-WFQFN Exposed Pad
• Frequency: 863MHz ~ 870MHz, 902MHz ~ 928MHz, 950MHz ~ 960MHz
• Data Rate - Maximum: 200kbps
• Modulation Or Protocol: FSK, OOK
• Applications: ISM
• Power - Output: 12.5dBm
• Sensitivity: -113dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 3mA
• Current - Transmitting: 25mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 863 MHz to 870 MHz, 902 MHz to 928 MHz, 950 MHz to 960 MHz
• Interface Type: SPI
• Noise Figure: - 112 dBc
• Output Power: - 8.5 dBm, + 12.5 dBm
• Operating Supply Voltage: 2.1 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Maximum Data Rate: 256 Kbps
• Maximum Supply Current: 25 mA
• Minimum Operating Temperature: - 40 C
• Modulation: FSK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2.1
The memory in the MRF89XA transceiver is imple-
mented as static RAM and is accessible via the SPI port.
Each memory location functionally addresses the
command, control, status or data/FIFO fields as shown
in Table 2-2 and Table 2-3. The control registers provide
TABLE 2-2:
 2010 Microchip Technology Inc.
General Parameters Configuration Registers: Size – 13 Bytes, Start Address – 00
Interrupt Parameters Configuration Registers: Size – 3 Bytes, Start Address – 13
Sl. No.
Sl. No.
10.
11.
12.
13.
14.
15.
16.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Memory Map for MRF89XA
Configuration/Control/Status
Registers
Register
Address
Register
Address
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
CONFIGURATION/CONTROL/STATUS REGISTER DESCRIPTION
GCONREG
DMODREG
FDEVREG
BRSREG
FLTHREG
FIFOCREG
R1CNTSREG
P1CNTSREG
S1CNTSREG
R2CNTSREG
P2CNTSREG
S2CNTSREG
PACONREG
FTXRXIREG
FTPRIREG
RSTHIREG
Register
Register
Name
Name
General Configuration Register
Data and Modulation Configuration
Register
Frequency Deviation Control
Register
Bit Rate Set Register
Floor Threshold Control Register
FIFO Configuration Register
R1 Counter Set Register
P1 Counter Set Register
S1 Counter Set Register
R2 Counter Set Register
P2 Counter Set Register
S2 Counter Set Register
Power Amplifier Control Register
FIFO, Transmit and Receive Interrupt
Request Configuration Register
FIFO Transmit PLL and RSSI
Interrupt Configuration Register
RSSI Threshold Interrupt Request
Configuration Register
Advance Information
Register Description
Register Description
control, status and configuration information. The
device address for the transceiver is done by indexing
the base address in the RAM memory. The registers
operate fundamentally on parameters common to
transmit and receive modes, Interrupt registers, receiver
parameters, Sync pattern, transmitter parameters,
crystal oscillator parameters and packet handler param-
eters. The FIFO serves as a temporary buffer for data
transmission and reception.
Transceiver mode, frequency band
selection, VCO trimming, PLL
frequency dividers selection
Modulation type, Data mode, OOK
threshold type, IF gain
Frequency deviation in FSK Transmit
mode
Operational bit rate
Floor threshold in OOK Receive mode
FIFO size and threshold
Value input for R1 counter
Value input for P1 counter
Value input for S1 counter
Value input for R2 counter
Value input for P2 counter
Value input for S2 counter
PA regulator output voltage
Interrupt request (‘0’ and ‘1’) in
Receive mode, interrupt request (‘1’)
in Transmit mode, interrupt request for
FIFO full, empty and overrun
FIFO fill method, FIFO fill, interrupt
request for TX start and end, interrupt
request for RSSI, PLL lock enable and
status
RSSI threshold for interrupt
Related Control Functions
Related Control Functions
MRF89XA
DS70622A-page 13