CSM56F801SLK Freescale Semiconductor, CSM56F801SLK Datasheet - Page 6

KIT LEARNING DSP 16BIT CSM56F801

CSM56F801SLK

Manufacturer Part Number
CSM56F801SLK
Description
KIT LEARNING DSP 16BIT CSM56F801
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of CSM56F801SLK

Processor To Be Evaluated
DSP56F801
Data Bus Width
16 bit
Interface Type
RS-232
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
D O C - 0 3 3 4 - 0 1 0 ,
CSM-56F801 OPERATION
The CSM-56F801 module provides input and output features to assist embedded application
development. Access to MPU port signals is available through connector J1. This connector
may also be used to input power to the module or to output power to attached modules. RS-
232 communications signals may also be input through connector J1. Care must be exercised
when using the J1 to power the module, as only regulated +3.3VDC (+/- 5%) should be
supplied to this connection
Five option jumpers and 3 cut-traces control module operation. Enabling a jumper option
requires installing a shunt across the associated header pins. Removing the shunt disables
the associated option. An option enabled by a cut-trace can be disabled by removing the
circuit trace between the cut-trace component pads. Use a sharp knife to cut the embedded
circuit trace. Be careful not to damage adjacent circuitry. To re-enable the option, simply
install a suitably sized 0-ohm resistor or piece of wire across the cut-trace component pads.
MEMORY MAP
The DSP56F801 utilizes two independent memory spaces, data and program, configured in a
Harvard architecture. RAM and Flash memory are used for on-chip data memory and on-chip
program memory. Refer to the DSP56F801 User Guide for details on accessing Program and
Data memory.
Table 1: Program Memory Map
NOTE: The first 4 logical addresses are a reflection of the first 4 physical addresses
of Boot Flash
0x0000 -
0x0003
0x0004 -
0x1FFF
0x 2000 -
0x7BFF
0x7C00 -
0x7FFF
0x8000 -
0x87FF
0x8800 –
0xFFFF
R E V
D
Freescale Semiconductor, Inc.
Boot Flash
Program Flash
Reserved
Program RAM
Boot Flash
Reserved
Program Memory – Mode 0A
6
D E C E M B E R
2 ,
2 0 0 5

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