XR21V1414IM48-F Exar Corporation, XR21V1414IM48-F Datasheet - Page 24
![IC UART FIFO USB QUAD 48TQFP](/photos/13/94/139467/xr21v1414im48-f_sml.jpg)
XR21V1414IM48-F
Manufacturer Part Number
XR21V1414IM48-F
Description
IC UART FIFO USB QUAD 48TQFP
Manufacturer
Exar Corporation
Type
USB UARTsr
Datasheet
1.XR21V1414IM48-F.pdf
(32 pages)
Specifications of XR21V1414IM48-F
Package / Case
48-TQFP
Features
*
Number Of Channels
1, UART
Fifo's
128 Byte
Protocol
USB 2.0
Voltage - Supply
3.3V
With Auto Flow Control
Yes
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
16 mA
Operating Supply Voltage
2.97 V to 3.63 V
No. Of Channels
4
Data Rate
12Mbps
Uart Features
Automatic Hardware And Software Flow Control, Half-Duplex Mode, Fractional Baud Rate Generator
Supply Voltage Range
2.97V To 3.63V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
1016-1303 - EVAL BOARD FOR XR21V1414IM
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
1016-1304
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XR21V1414IM48-F
Manufacturer:
EXAR
Quantity:
5 000
Company:
Part Number:
XR21V1414IM48-F
Manufacturer:
Exar Corporation
Quantity:
10 000
Part Number:
XR21V1414IM48-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR21V1414
4-CH FULL-SPEED USB UART
This register reports any errors that may have occurred on the line such as break, framing, parity and overrun.
ERROR_STATUS[2:0]: Reserved
These bits are reserved. Any values read from these bits should be ignored.
ERROR_STATUS[3]: Break error
ERROR_STATUS[4]: Framing Error
ERROR_STATUS[5]: Parity Error
ERROR_STATUS[6]: Overrun Error
ERROR_STATUS[7]: Break Status
Writing a non-zero value to this register causes a break condition to be generated continuously until the
register is cleared. If data is being shifted out of the TX pin, the data will be completely shifted out before the
break condition is generated.
XCVR_EN_DELAY[3:0]: Turn-around delay
This is the number of bit times to wait before changing the direction of the transceiver from transmit to receive
when half-duplex mode is enabled.
XCVR_EN_DELAY[3:0]: Reserved
These bits are reserved and should be ’0’.
3.3.8
3.3.9
3.3.10
Logic 0 = No break condition
Logic 1 = A break condition has been detected (clears after read).
Logic 0 = No framing error
Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected.
Logic 0 = No parity error
Logic 1 = A parity error has been detected (clears after read).
Logic 0 = No overrun error
Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received.
Logic 0 = Break condition is no longer present.
Logic 1 = Break condition is currently being detected.
ERROR_STATUS Register Description - Read-only
TX_BREAK Register Description (Read/Write)
XCVR_EN_DELAY Register Description (Read/Write)
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