XR88C681J-F Exar Corporation, XR88C681J-F Datasheet - Page 76

• Manufacturer Part Number: XR88C681J-F
• Description: IC UART CMOS DUAL 44PLCC
• Manufacturer: Exar Corporation
• Type: CMOS Dual Channel UARTr

Specifications of XR88C681J-F

• Number Of Channels: 2, DUART
• Package / Case: 44-LCC (J-Lead)
• Features: *
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 4.75 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Propagation Delay Time Ns: 400 ns
• No. Of Channels: 2
• Supply Voltage Range: 4.75V To 5.25V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1329

In this mode:
1. Received data is transmitted on the channel’s TXDn
2. Received data is not sent to the CPU and the error
3. Parity and framing (stop bits) are transmitted as
4. The receiver must be enabled.
5. The received break is echoed as received until the
MR2n[5] - Transmitter Request-to-Send Control
Ordinarily, the RTS (Request to Send) output is asserted
or negated by invoking the “SET OUTPUT PORT BITS
COMMAND”
COMMAND” in the appropriate manner, by the system
software.
Channel Transmitter to negate RTS automatically, one bit
output
status conditions are not checked.
received.
next valid start bit is detected.
Rev. 2.11
Serial Data
Incoming
Receive Holding
Register
However, setting MR2n[5] = 1 allows the
or
RXDn
“CLEAR
Figure 41. A Block Diagram Depicting Remote Loopback Mode
Note: The CPU has no access to the Serial Data during Remote Loopback Mode.
Receive Shift Register
OUTPUT
RXCn
PORT
BITS
76
time after the characters in the TSR and THR have been
transmitted and are now empty.
Figure 44
Transmitter-Controlled Request-to-Send configuration
would function.
MR2n[4] - Clear to Send Control
If this bit is a 0, the channels -CTSn input (IP0 for Channel
A, or IP1 for Channel B) has no effect on the transmitter. If
the bit is a “1”, the transmitter will check the state of its
-CTSn input each time is it ready to send a character. If
-CTSn is low (or “true”), the character is transmitted. If
-CTSn is high (or negated), TXDn remains in the marking
state and the transmission of the next character is
delayed until -CTSn goes low. Changes in the -CTSn
input while a character is being serialized do not affect
transmission of that character.
further illustrated in Figure 42 and Figure 44.
Transmit Shift Register
presents
TXCn
a
diagram illustrate
TXDn
Transmit Holding
This phenomenon is
Register
Serial Data
Outgoing
how a