MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 554

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Queued Analog-to-Digital Converter (QADC)
28-16
Bit(s)
12–8
6–0
15
14
13
7
RESUME
MQ2[12:8]
Name
SSE2
CIE2
PIE2
MQ2
BQ2
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Queue 2 completion software interrupt enable. Enables an interrupt request upon
completion of queue 2. The interrupt request is initiated when the conversion is
complete for the last CCW in queue 2.
1 Enable queue 2 completion interrupt.
0 Disable queue 2 completion interrupt.
Queue 2 pause interrupt enable. Enables an interrupt request when queue 2 enters
the pause state. The interrupt request is initiated when conversion is complete for a
CCW that has the pause bit set.
1 Enable the queue 2 pause interrupt.
0 Disable the queue 2 pause interrupt.
Queue 2 single-scan enable. Enables a single-scan of queue 2 after a trigger event
occurs. SSE2 may be set during the same write cycle that sets the MQ2 bits for one
of the single-scan queue operating modes. The single-scan enable bit can be written
to 1 or 0, but is always read as a 0, unless the QADC is in test mode. The QADC clears
SSE2 when the single-scan is complete.
1 Allow a trigger event to start queue 2 in a single-scan mode.
0 Trigger events are ignored for queue 2 single-scan modes.
Selects the operating mode for queue 2.
which enable different queue 2 operating modes.
Selects the resumption point for queue 2 after its operation is suspended due to a
queue 1 trigger event. If RESUME is changed during the execution of queue 2, the
change is not recognized until an end-of-queue condition is reached or the operating
mode of queue 2 is changed.
1 After suspension, begin execution with the aborted CCW in queue 2.
0 After suspension, begin execution with the first CCW of queue 2 or the current
Beginning of queue 2. Denotes the CCW location where queue 2 begins. This allows
the length of queue 1 and queue 2 to vary. The BQ2 field also serves as an
end-of-queue condition for queue 1.
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE2)
Externally triggered rising edge single-scan mode
Externally triggered falling edge single-scan mode
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
Interval timer single-scan mode: time = QCLK period x 2
subqueue of queue 2.
Table 28-8. QACR2 Field Descriptions
Table 28-9. Queue 2 Operating Modes
Operating Modes
Description
Table 28-9
shows the bits in the MQ1 field
7
8
9
10
11
12
Freescale Semiconductor