MCF5216CVF66 Freescale Semiconductor, MCF5216CVF66 Datasheet - Page 212

• Manufacturer Part Number: MCF5216CVF66
• Description: IC MPU 32BIT COLDF 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5216CVF66

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Operating Temperature Range: -40°C To +85°C
• No. Of Pins: 256
• Rohs Compliant: No
• Package: 256MA-BGA
• Device Core: ColdFire
• Family Name: MCF521x
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 142
• Interface Type: QSPI/UART/I2C/CAN
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 8
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Edge Port Module (EPORT)
11.4.2.2 EPORT Data Direction Register (EPDDR)
11-4
Bit(s)
Bit(s)
15–2
1–0
7–1
0
Address
Reset
EPDDx
EPPAx
Name
Name
Field
R/W
—
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
EPDD7
Figure 11-3. EPORT Data Direction Register (EPDDR)
7
EPORT pin assignment select fields. The read/write EPPAx fields configure EPORT
pins for level detection and rising and/or falling edge detection.
Pins configured as level-sensitive are inverted so that a logic 0 on the external pin
represents a valid interrupt request. Level-sensitive interrupt inputs are not latched. To
guarantee that a level-sensitive interrupt request is acknowledged, the interrupt
source must keep the signal asserted until acknowledged by software. Level
sensitivity must be selected to bring the device out of stop mode with an IRQx
interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for
interrupt generation. A pin configured for edge detection can trigger an interrupt
regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt
controller module. EPPAR functionality is independent of the selected pin direction.
Reset clears the EPPAx fields.
00 Pin IRQx level-sensitive
01 Pin IRQx rising edge triggered
10 Pin IRQx falling edge triggered
11 Pin IRQx both falling edge and rising edge triggered
Reserved, should be cleared.
Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing
any bit in EPDDR configures the corresponding pin as an input. Pin direction is
independent of the level/edge detection configuration. Reset clears EPDD7-EPDD1.
To use an EPORT pin as an external interrupt request source, its corresponding bit in
EPDDR must be clear. Software can generate interrupt requests by programming the
EPORT data register when the EPDDR selects output.
1 Corresponding EPORT pin configured as output
0 Corresponding EPORT pin configured as input
Reserved, should be cleared.
Table 11-3. EPPAR Field Descriptions
EPDD6
Table 11-4. EPDD Field Descriptions
6
EPDD5
5
IPSBAR + 0x0013_0002
R/W
0000_0000
EPDD4
4
Description
Description
EPDD3 EPDD2 EPDD1
3
2
1
Freescale Semiconductor
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R
0