AT91SAM7S256C-MU Atmel, AT91SAM7S256C-MU Datasheet - Page 764

• Manufacturer Part Number: AT91SAM7S256C-MU
• Description: IC ARM7 MCU 32BIT 256K 64-QFN
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S256C-MU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT91
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: SPI, TWI, USART, USB
• Maximum Clock Frequency: 55 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7S256-MU; AT91SAM7S256-MU

754
Version
6175F
AT91SAM7S Series Preliminary
Comments (Continued)
SPI, Figure 28-9 ”Slave Mode Functional Block Diagram” page 272, FLOAD removed
Section 28.6.3 ”Master Mode Operations” change to SPI_RDR information
Section 28.7.1 ”SPI Control Register” added information to bit description ”SWRST: SPI Software Reset”
page 14.
Section 28.7.9 ”SPI Chip Select Register” corrected equation in ”DLYBCT: Delay Between Consecutive
Transfers” page 25.
Section 28.6.3.8 ”Mode Fault Detection” updated
SSC, Section 31.6.6.1 ”Compare Functions” updated
TC, Table 32-1, “Timer Counter Clock Assignment,” on page 389 has been added.
Section 32.5.4 ”External Event/Trigger Conditions” TIOB defined as external event signal..... updated
”EEVT: External Event Selection” page 412, TIOB chosen as external event signal..... updated in footnote
TWI, ”Two-wire Interface (TWI) User Interface” page 294, UNRE and OVRE bit fields removed from TWI
Status and Interrupt register tables.
UDP, Figure 34-2 on page 446 updated,
Section 34.4.1 ”USB Device Transceiver” and Section 34.4.2 ”VBUS Monitoring” page 446 added.
Section 34.5.1.2 ”USB Bus Transactions” updated
Section 34.5.1.3 ”USB Transfer Event Definitions” updated with endpoint information.
Section 34.5.2.2 ”Data IN Transaction” Endpoint use updated.
Section 34.5.2 ”Handling Transactions with USB V2.0 Device Peripheral” page 450, Section reworked,
warnings added.
Section 34.5.3 ”Controlling Device States” page 458, Section reworked and Section 34.5.3.1 ”Not
Powered State” and Section 34.5.3.2 ”Entering Attached State” page 459 added.
Section 34.6 ”USB Device Port (UDP) User Interface”
Section 34.6.2 ”UDP Global State Register” page 464,updated.
Section 34.6.10 ”UDP Endpoint Control and Status Register” page 473, updated
Corrections, improvements, additions and deletions throughout section, new source document.
Section Section 34.5.3.8 ”Sending a Device Remote Wakeup” replaces title: “Sending an External
Resume”.
WAKEUP bit shown in interrupt registers:Section 34.6.4 on page 466 thru Section 34.6.8 on page 471.
RMWUPE, RSMINPR, ESR bits removed from Section 34.6.2 ”UDP Global State Register”.
NOTE: pertinent to USB pullup effect on USB Reset added to Section 34.6.12 ”UDP Transceiver Control
Register”.
6175K–ATARM–30-Aug-10
Change
Request
Ref.
#1542
#1543
#1676
IP update
#2470
#2704
#2470
source file
update
3288