FDML7610S Fairchild Semiconductor, FDML7610S Datasheet - Page 8

• Manufacturer Part Number: FDML7610S
• Description: MOSFET N-CH 30V DUAL 8-MLP
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r

Specifications of FDML7610S

• Fet Type: 2 N-Channel (Dual)
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 7.5 mOhm @ 12A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 12A, 17A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 28nC @ 10V
• Input Capacitance (ciss) @ Vds: 1750pF @ 15V
• Power - Max: 800mW, 900mW
• Mounting Type: Surface Mount
• Package / Case: *
• Module Configuration: Dual
• Transistor Polarity: N Channel
• Continuous Drain Current Id: 30A
• Drain Source Voltage Vds: 30V
• On Resistance Rds(on): 0.006ohm
• Rds(on) Test Voltage Vgs: 10V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDML7610STR

©2010 Fairchild Semiconductor Corporation
FDML7610S Rev.C1
Typical Characteristics (Q2 SyncFET)
10
80
60
40
20
8
6
4
2
0
Figure 19. Gate Charge Characteristics
0
300
100
Figure 21.
25
0
10
1
0.001
I
Limited by package
D
= 17A
Current vs Case Temperature
V
GS
10
50
= 4.5 V
T
Maximun Continuous Drain
C
Q
,
CASE TEMPERATURE (
g
V
, GATE CHARGE (nC)
DD
V
20
GS
75
= 10 V
0.01
V
= 10 V
DD
= 20 V
Figure 23. Single Pulse Maximum Power Dissipation
100
30
V
DD
R
= 15 V
o
θ
C )
JC
125
40
= 3.5
0.1
o
t, PULSE WIDTH (sec)
C/W
150
50
T
J
= 25
8
1
o
C unless otherwise noted
5000
1000
100
0.01
100
60
0.1
10
0.1
1
0.01
f = 1 MHz
V
GS
Figure 20. Capacitance vs Drain
THIS AREA IS
LIMITED BY r DS
SINGLE PULSE
T
R
T
J
A
θ
Figure 22. Forward Bias Safe
JA
= 0 V
= MAX RATED
= 25
= 140
10
V
V
DS
o
C
DS
0.1
, DRAIN TO SOURCE VOLTAGE (V)
to Source Voltage
o
, DRAIN to SOURCE VOLTAGE (V)
C/W
Operating Area
(
on
)
1
1
100
SINGLE PULSE
R
T
A
θ
JA
= 25
= 140
10
o
C
10
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o
C
C/W
C
rss
C
DC
1s
10 ms
100 ms
1 ms
10s
oss
iss
100
1000
30
200