MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 31

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The MAXQ7665A–MAXQ7665D are low-cost, high-per-
formance, CMOS, fully static, 16-bit µCs with flash mem-
ory and are members of the MAXQ family of µCs. The
MAXQ7665A–MAXQ7665D are structured on a highly
advanced, accumulator-based, 16-bit RISC architec-
ture. Fetch and execution operations are completed in
one cycle without pipelining, because the instruction
contains both the operation code and data. The result is a
streamlined 8 million instructions-per-second (MIPS) µC.
The highly efficient core is supported by a 16-level
hardware stack, enabling fast subroutine calling and
task switching. Data can be quickly and efficiently
manipulated with three internal data pointers. Multiple
data pointers allow more than one function to access
data memory without having to save and restore data
pointers each time. The data pointers can automatically
increment or decrement following an operation, elimi-
nating the need for software intervention. As a result,
application speed is greatly increased.
The instruction set is composed of fixed-length, 16-bit
instructions that operate on registers and memory loca-
tions. The instruction set is highly orthogonal, allowing
arithmetic and logical operations to use any register
along with the accumulator. Special-function registers
(also called peripheral registers) control the peripherals
and are subdivided into register modules. The family
architecture is modular, so that new devices and mod-
ules can reuse code developed for existing products.
The architecture is transport-triggered. This means that
writes or reads from certain register locations can also
cause side effects to occur. These side effects form the
basis for the higher level operation codes defined by the
assembler, such as ADDC, OR, JUMP, etc. The operation
codes are actually implemented as MOVE instructions
between certain register locations, while the assembler
handles the encoding, which need not be a concern to
the programmer.
The 16-bit instruction word is designed for efficient exe-
cution. Bit 15 indicates the format for the source field of
the instruction. Bits 0 to 7 of the instruction represent the
MAXQ Core Architecture
______________________________________________________________________________________
Instruction Set
16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
source for the transfer. Depending on the value of the
format field, this can either be an immediate value or a
source register. If this field represents a register, the
lower 4 bits contain the module specifier and the upper
4 bits contain the register index in that module.
Bits 8 to 14 represent the destination for the transfer.
This value always represents a destination register, with
the lower 4 bits containing the module specifier and the
upper 3 bits containing the register subindex within that
module. Any time that it is necessary to directly select
one of the upper 24 registers as a destination, the pre-
fix register, PFX, is needed to supply the extra destina-
tion bits. This prefix register write is inserted
automatically by the assembler and requires only one
additional execution cycle.
The MAXQ7665A–MAXQ7665D incorporate several
memory areas:
• 8KB (4K x 16) utility ROM
• Up to 128KB (64K x 16) of flash memory for program
• 512 bytes (256 x 16) of SRAM for storage of temporary
• 16-level stack memory for storage of program return
The memory is arranged by default in a Harvard archi-
tecture, with separate address spaces for program and
data memory (see Figure 14). A special mode allows
data memory to be mapped into program space, permit-
ting code execution from data memory. In addition,
another mode allows program memory to be mapped
into data space, permitting code constants to be
accessed as data memory.
The incorporation of flash memory allows the devices to
be reprogrammed, eliminating the expense of throwing
away one-time programmable devices during develop-
ment and field upgrades (see Figure 15 for the flash
memory sector maps). Flash memory can be password
protected with a 16-word key, denying access to pro-
gram memory by unauthorized individuals.
storage
variables
addresses and general-purpose use
Memory Organization
31