MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 22

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
During power-up, RESET is held low once DV
above +1.0V. All internal register bits are set to their
default, POR state after DV
approximately +1.2V. This includes the VDBR bits
which reset to 00b, resulting in a default, DV
brownout reset (BOR) threshold in the +2.7V to +2.99V
range following POR. Once DV
DV
starts driving the power-up counter, and 8.6ms (typ)
later, the RESET pin is released and allowed to go high
if nothing external is holding it low. An important sys-
tem-design consideration at power-up is the DV
ramp-up rate should be at least 35mV/ms between
+2.7V and +3.0V. This ensures RESET is not released
before DV
of +3.0V. After DV
RESET is released, the µC jumps to the reset vector
Figure 5. DV
22
DD
_______________________________________________________________________________________
brownout threshold, the 7.6MHz RC oscillator
BROWNOUT
BROWNOUT
INTERRUPT
TRIGGER
TRIGGER
DD
RESET
POINT
POINT
DD
NOMINAL
DV
DD
Brownout Interrupt Detection
reaches a minimum flash operating level
(+3.3V)
+2.84V
+2.77V
DGND
DVLVL FLAG
(ASR[14])
DVBI FLAG
(ASR[4])
+3.13V
+3.06V
DD
has reached a valid level and
DD
exceeds a threshold of
DD
BROWNOUT
INTERRUPT
rises above this
DD
INTERNAL RESET
BROWNOUT
RESET
RESET OUTPUT
rises
DD
DD
(8000h in the utility ROM), and the desired BOI and
BOR threshold values can be set by the user through
the VIOBI, VDBI, and VDBR bits.
If a valid DV
the VDBI bits), an interrupt is generated. This offers
the possibility of limited software cleanup before the
DV
depends on the VDBI and VDBR brownout threshold
bit settings, the size of the DV
and the application-dependent, µC power manage-
ment and software cleanup tasks. Note that if the
internal, +3.3V linear regulator is being used to pro-
vide DV
ble by using the DV
warning that the regulator’s DV
age is falling, and its DV
drop (unless DV
DD
FLAG ARBITRARILY
CLEARED BY µC
BOR occurs. The amount of cleanup time
DD
, additional software cleanup time is possi-
BOR STATE
DD
DDIO
drops below its BOI threshold (set by
POWER-UP*
(8.6ms)
DELAY
DDIO
recovers).
DD
brownout monitor as an early
VDBE BIT SET BY µC
*POWER-UP DELAY IS ONLY
PRESENT WHEN DV
BELOW ~1.2V
(+3.3V) will subsequently
DD
DDIO
DV
RESET THRESHOLD
RANGE VDBR[1:0] = 01
DD
bypass capacitors,
DV
INTERRUPT
THRESHOLD RANGE
VDBI[1:0] = 01
BROWNOUT
DD
(+5V) input volt-
BROWNOUT
DD
DROPS