MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 17

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

PIN
33
34
35
36
37
38
40
41
42
43
44
45
46
47
48
—
P 0.5/D AC LOAD
P0.4/ADCCNV
______________________________________________________________________________________
P0.1/TMS
P0.3/TCK
P0.2/TDI
REGEN
RESET
NAME
AIN15
AIN14
AIN13
AIN12
XOUT
DV
AV
XIN
EP
DD
DD
Port 0 Data 1/JTAG Test Mode Select. P0.1 is a general-purpose digital I/O with interrupt/wake-
up capability. TMS is the JTAG test mode, select input.
Port 0 Data 2/JTAG Serial Test Data Input. P0.2 is a general-purpose digital I/O with
interrupt/wake-up capability. TDI is the JTAG serial test, data input.
Port 0 Data 3/JTAG Serial Test Clock Input. P0.3 is a general-purpose digital I/O with
interrupt/wake-up capability. TCK is the JTAG serial test, clock input.
Port 0 Data 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O. ADCCNV is
firmware configurable for a rising or falling edge start/convert to trigger ADC conversions.
Port 0 Data 5/DAC Data Register Load/Update Input. P0.5 is a general-purpose digital I/O with
interrupt/wake-up capability. DACLOAD is firmware configurable for a rising or falling edge to
update the DACOUT register.
Active-Low Linear Regulator Enable Input. Connect REGEN to GNDIO to enable the linear
regulator. Connect to DV
Digital Supply Voltage. DV
internally connected to the output of the internal 3.3V linear regulator. Disable the internal
regulator to connect DV
DV
DV
Reset Input and Output. Active-low open-drain input/output with internal 360kΩ pullup to DV
Drive low to reset the µC. RESET is low during power-up reset and during DV
conditions.
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal
operation. Leave XOUT unconnected if XIN is driven with an external clock source. XOUT is not
driven when using the internal RC oscillator.
High-Frequency Crystal Input. Connect an external crystal or resonator to XIN and XOUT for
normal operation, or drive XIN with an external clock source. XIN is not driven when using the
internal RC oscillator.
Analog Supply Voltage Input. Connect AV
0.1µF capacitor placed as close as possible to the device.
Analog Input Channel 15. AIN15 is multiplexed to the PGA as a differential input with AIN14.
Analog Input Channel 14. AIN14 is multiplexed to the PGA as a differential input with AIN15.
Analog Input Channel 13. AIN13 is multiplexed to the PGA as a differential input with AIN12.
Analog Input Channel 12. AIN12 is multiplexed to the PGA as a differential input with AIN13.
Exposed Pad. EP is internally connected to AGND. Connect EP to AGND externally.
16-Bit RISC Microcontroller-Based
DD
DD
with a 0.1µF capacitor. Place both bypass capacitors as close as possible to the device.
to DGND with a 4.7µF ±20% capacitor with a maximum ESR of 0.5Ω. In addition, bypass
Smart Data-Acquisition Systems
DD
DDIO
DD
to an external supply. When using the on-chip linear regulator, bypass
supplies the internal digital core and flash memory. DV
to disable the linear regulator.
DD
FUNCTION
to a +5V supply. Bypass AV
Pin Description (continued)
DD
to AGND with a
DD
brownout
DD
is
DD
.
17