MAXQ7665BATM+ Maxim Integrated Products, MAXQ7665BATM+ Datasheet - Page 28

• Manufacturer Part Number: MAXQ7665BATM+
• Description: IC MCU-BASED DAS 16BIT 48-TQFN
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ7665BATM+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 8
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 256 x 16
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 8x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 48-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16-Bit RISC Microcontroller-Based
Smart Data-Acquisition Systems
detection. Table 1 summarizes the operating characteris-
tics as well as the maximum baud rate of each mode.
The joint test action group (JTAG) IEEE 1149.1 stan-
dard defines a unique method for in-circuit testing and
programming. The MAXQ7665A–MAXQ7665D conform
to this standard, implementing an external test access
port (TAP) and internal TAP controller for communica-
tion with a JTAG bus master, such as an automatic test
equipment (ATE) system. For detailed information on
Figure 11b. UART Asynchronous Mode (Mode 1)
Table 1. Operating Characteristics and Mode Baud Rate
28
Mode 0
Mode 1
Mode 2
Mode 3
MODE
_______________________________________________________________________________________
SMOD
SYSCLK
DIVIDE
BY 4
Asynchronous
Asynchronous
Asynchronous
Synchronous
BAUD CLOCK
GENERATOR
0
TYPE
1
SCON0.1
FLAG =
TI
DIVIDE
BY 16
JTAG Interface Bus
RDSBUF
LDSBUF
SCON0.0
FLAG =
Baud generation
Baud generation
BAUD CLOCK
32 or 64 clock
RI
4 or 12 clock
BAUD
CLOCK
RESET
BUFFER
SERIAL
SERIAL
INTERRUPT
LOAD
1
SERIAL I/O
CONTROL
TRANSMIT SHIFT REGISTER
DIVIDE
BY 16
START BITS
SBUF0
DETECTION
BUFFER
SHIFT
SERIAL
N/A
LOAD
READ
1
1
1
BIT
the TAP and TAP controller, refer to IEEE Standard
1149.1 on the IEEE website at http://standards.ieee.org.
The JTAG on the MAXQ7665A–MAXQ7665D is used for
in-circuit emulation and debug support, but does not
support boundary scan test capability.
The TAP controller communicates synchronously with
the host system (bus master) through four digital I/O
pins: test mode select (TMS), test clock (TCK), test
data input (TDI), and test data output (TDO). The inter-
nal TAP module consists of several shift registers and a
SI
0
DATA BITS
SCON0.2
S0
RB8 =
RD
8 + 1
8 + 1
RECEIVE SHIFT REGISTER
8
8
LATCH
RECEIVE DATA BUFFER
DATA BUS
STOP BITS
N/A
1
1
1
OUTPUT
UTX
SBUF0
INPUT
URX
WR
MAX BAUD RATE AT
250kbps
250kbps
250kbps
2Mbps
8MHz