DS89C420-MNL Maxim Integrated Products, DS89C420-MNL Datasheet - Page 7

• Manufacturer Part Number: DS89C420-MNL
• Description: IC MCU ULTRA 33MHZ HP 40-DIP
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C420-MNL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Note 1: The system clock frequency is dependent on the oscillator frequency and the setting of the clock-divide control bits (CD1 and CD0) and
Note 2: External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in the clock control register. The terms
Note 3: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN, WR, and RD is limited to 60pF. XTAL1 and XTAL2 load
Figure 1. Non-Page Mode Timing
XTAL1
PSEN
Port 0
Port 2
ALE
RD
WR
the crystal multiplier control bits (4X/2X and CTM) in the PMR register. The term “1 / t
through the use of the table given below.
“t
capacitance is dependent on the frequency of the selected crystal.
MD2
STC1
0
0
0
0
1
1
1
1
4X/2X
X
X
X
1
0
, t
STC2
MD1
1
0
0
1
1
, t
1
0
0
STC3
LSB
CD1
0
0
0
1
1
MSB
t
” used in the variable timing table are calculated through the use of the table given below.
LLIV
t
MD0
t
AVLL
AVLL2
0
1
0
1
0
1
0
1
t
t
t
t
CLCL
t
PXIX
LLAX
PXIZ
LLPL
CD0
MOVX
0
0
1
0
1
MOVX INSTRUCTION TIME
(MACHINE CYCLES)
4 Oscillator Cycles
2 Oscillator Cycles
Reserved
1 Oscillator Cycle
1 / 1024 Oscillator Cycle
LSB
t
NUMBER OF OSCILLATOR CYCLES PER
AVIV0
MSB
10
11
12
5
9
2
3
4
t
PLPH
t
SYSTEM CLOCK (1 / t
AVWL2
MOVX
t
PLIV
t
RLDV
t
LSB
t
AVDV2
7 of 47
AVDV0
MSB
t
(t
t
AVLL3
t
LHLL
STC1
CLCL
10
14
18
22
26
0
2
6
t
t
LLAX3
RLRH
CLCL
)
DATA
t
)
LLDV
(t
t
STC2
CLCL
0
1
1
1
5
5
5
5
t
LSB
RHDX
)
t
t
AVIV2
RHDZ
CLCL
MSB
(t
t
” used in the variable timing table is calculated
t
STC3
CLCL
PLAZ
4
4
4
4
0
0
0
0
OPCODE
)
t
AVWL0
(t
t
CLCL
STC4
1
1
1
1
0
0
0
0
LSB
)
t
t
WHQX
t
WHLH
(t
t
t
MSB
WLWH
t
LLAX2
LLWL
CLCL
STC5
t
0
1
1
1
1
1
1
1
QVWX
DATA
)