DS89C420-MNL Maxim Integrated Products, DS89C420-MNL Datasheet - Page 41

• Manufacturer Part Number: DS89C420-MNL
• Description: IC MCU ULTRA 33MHZ HP 40-DIP
• Manufacturer: Maxim Integrated Products
• Series: 89Cr

Specifications of DS89C420-MNL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, SIO, UART/USART
• Peripherals: Power-Fail Reset, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Table 14. Effect of Clock Mode on Timer Operation (in Number of Oscillator Clocks)
x = don’t care
RING OSCILLATOR
A ring oscillator, which typically runs at 10MHz, allows the processor to recover instantly from the stop mode.
When the system is in stop mode the crystal is disabled. When stop mode is removed, the crystal requires a period
of time to start up and stabilize. To allow the system to begin immediate execution of software following the
removal of the stop mode, the ring oscillator is used to supply a system clock until the crystal startup time is
satisfied. Once this time has passed, the ring oscillator is switched off and the system clock is switched over to the
crystal oscillator. This function is programmable and is enabled by setting the RGSL bit (EXIF.1) to logic 1. When it
is logic 0, the processor delays software execution until after the 65,536 crystal clock periods. To allow the
processor to know whether it is being clocked by the ring or the crystal oscillator, an additional bit, termed the
RGMD bit, indicates which clock source is being used. When the processor is running from the ring, the clock-
divide control bits (CD1 and CD0 in the PMR register) are locked into the divide-by-1 mode (CD1:CD0 = 10b). The
clock-divide control bits cannot be changed from this state until after the system clock transitions to the crystal
oscillator (RGMD = 0).
Note: The watchdog is permanently connected to the crystal oscillator and continues to run at the external clock
rate. The ring oscillator does not drive it.
IDLE MODE
Idle mode suspends the processor by holding the program counter in a static state. No instructions are fetched and
no processing occurs. Setting the IDLE bit (PCON.0) to logic 1 invokes idle mode. The instruction that executes
this step is the last instruction prior to freezing the program counter. Once in Idle mode, all resources are preserved
but all peripheral clocks remain active, and the timers, watchdog, serial ports, and power monitor functions
continue to operate, so that the processor can exit the idle mode using any interrupt sources that are enabled. The
oscillator-detect circuit also continues to function when enabled. The IDLE bit is cleared automatically once idle
mode is exited. On returning from the interrupt vector using the RETI instruction, the next address is the one that
immediately follows the instruction that invoked the idle mode. Any processor resets also remove the idle mode.
STOP MODE
The stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication
are stopped, and no processing is possible.
Stop mode is invoked by setting the STOP bit (PCON.1) to logic 1. The processor enters the stop mode on the
instruction that sets the bit. The processor can exit stop mode by using any of the six external interrupts that are
enabled.
4X/2X, CD1, CD0
100
000
x01
x10
x11
1 (reserved)
MACHINE
1 (default)
CYCLES
CYCLE
OSC.
1,024
PER
0.25
0.5
12,288 4,096 1,024
OSC. CYCLES PER
12
12
12
00
TIMERS (0, 1, 2)
TxMH, TxM
CLOCK
01
—
=
1
2
4
0.25
0.5
1x
1
41 of 47
T2MH, T2M = xx
OSC. CYCLES
PER TIMER 2
GENERATOR
BAUD RATE
CLOCK
2,048
—
2
2
2
SM2 = 0 SM2 = 1 SMOD = 0 SMOD = 1
12,288
OSC. CYCLES
PORT CLOCK
PER SERIAL
12
3
6
MODE 0
—
4,096
1
2
4
OSC. CYCLES PER
65,536
CLOCK MODE 2
SERIAL PORT
64
64
64
—
32,768
32
32
32