DS89C420-QCL Maxim Integrated Products, DS89C420-QCL Datasheet

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... PART TEMP RANGE DS89C420-MNG -40°C to +85°C DS89C420-QNG -40°C to +85°C DS89C420-ENG -40°C to +85°C DS89C420-MCL 0°C to +70°C DS89C420-QCL 0°C to +70°C DS89C420-ECL 0°C to +70°C DS89C420-MNL -40°C to +85°C DS89C420-QNL -40°C to +85°C DS89C420-ENL -40°C to +85°C Pin Configurations appear at end of data sheet. ...

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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Voltage Range on V Relative to Ground CC Operating Temperature Range Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to ...

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Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: Active current is measured with a 25MHz/33MHz clock source driving XTAL1, V Note 4: Idle mode current ...

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... STC3 STC3 0. 1. CLCL CLCL 1. 2. CLCL CLCL 1. 2. CLCL CLCL + STC4 STC4 1. 2. CLCL CLCL + STC4 STC4 CLCL CLCL DS89C420 Ultra-High-Speed Microcontroller PAGE MODE 2 NON-PAGE MODE MAX MIN MAX MIN 1. 1. CLCL CLCL t t STC3 STC3 0. CLCL CLCL 0. CLCL ...

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... CLCL CLCL CLCL CLCL t t STC1 STC1 CLCL CLCL t t STC1 STC1 CLCL CLCL t t STC1 STC1 DS89C420 Ultra-High-Speed Microcontroller PAGE MODE 2 NON-PAGE MODE MAX MIN MAX MIN CLCL CLCL CLCL 1.5t - CLCL 20 2.5t - CLCL CLCL CLCL CLCL t t STC1 STC1 ...

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... CLCL CLCL + STC2 STC2 STC2 STC2 0. 1. CLCL CLCL + STC5 STC5 - STC2 STC2 STC2 STC2 DS89C420 Ultra-High-Speed Microcontroller PAGE MODE 2 NON-PAGE MODE MAX MIN MAX MIN 3.5t - 3.0t - CLCL CLCL STC1 STC1 CLCL CLCL CLCL CLCL STC2 STC2 STC2 STC2 1 ...

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Note 1: The system clock frequency is dependent on the oscillator frequency and the setting of the clock-divide control bits (CD1 and CD0) and the crystal multiplier control bits (4X/2X and CTM) in the PMR register. The term “1 / ...

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Figure 2. Page-Mode 1 Timing XTAL1 t CLCL ALE t AVLL2 PSEN AVIV2 Port 0 MOVX OPCODE Port 2 LSB LSB LSB Figure 3. Page-Mode 2 Timing XTAL1 t CLCL ALE t AVLL t AVLL2 PSEN t ...

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EXTERNAL CLOCK CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C.)* CC A PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SERIAL PORT MODE 0 TIMING CHARACTERISTICS (V = 4.5V to 5.5V; T ...

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Figure 4. Serial Port Timing SERIAL PORT (SYNCHRONOUS MODE) SM2 = 1 TDX CLOCK = XTAL FREQ/4 ALE PSEN t QVXH WRITE TO SBUF RXD DATA OUT TXD CLOCK TI WRITE TO SCON TO CLEAR RI RXD DATA IN TXD ...

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POWER CYCLE TIMING CHARACTERISTICS (V = 4.5V to 5.5V -40°C to +85°C.) (Note PARAMETER Crystal Startup Time Power-On Reset Delay Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: ...

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... This condition also serves as an input state, since any external circuit that writes to the port overcomes the weak pullup. When software writes any port pin, the DS89C420 activates a strong pulldown that remains on until either written or a reset occurs ...

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... P3.0–P3.7 overcomes the weak pullup. When software writes any port pin, the DS89C420 activates a strong pulldown that remains on until either written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. ...

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... DS89C420 DETAILED DESCRIPTION The DS89C420 is pin compatible with all three packages of the standard 8051 and includes standard resources such as three timer/counters, four 8-bit I/O ports, and a serial port. It features 16kB of in-system programmable flash memory, which can be programmed in-system from an I/O port using a built-in program memory loader. It can also be loaded externally using standard commercially available programmers ...

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... Therefore, they required the same amount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two oscillator cycles but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts, they now have different execution times ...

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... RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O PORTS The DS89C420 offers four 8-bit I/O ports. Each I/O port is represented by an SFR location, and can be written or read. The I/O port has a latch that contains the value written by software. COUNTER/TIMERS Three 16-bit timer/counters are available in the DS89C420. Each timer is contained in two SFR locations that can be read or written by software. The timers are controlled by other SFRs described in the “ ...

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Table 1. Special Function Registers REGISTER ADDR BIT 7 P0 80h P0.7 SP 81h — DPL 82h — DPH 83h — DPL1 84h — DPH1 85h — DPS 86h ID1 PCON 87h SMOD_0 TCON 88h TF1 TMOD 89h GATE TL0 ...

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... If the maximum address of on- chip program or data memory is exceeded, the DS89C420 performs an external memory access using the expanded memory bus. The PSEN signal goes active-low to serve as a chip enable or output enable when performing a code fetch from external program memory ...

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... The program memory ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the DS89C420 to act as a bootloader for an external flash or NV SRAM. It also enables the use of the overlapping external program spaces. 256 bytes of on-chip RAM serve as a register area and program stack, which are separated from the data memory ...

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... Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For example, assume that a DS89C420 is executing instructions from internal program memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software reconfigures the ROMSIZE register to 4kB (0000h– ...

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... Software selects the data pointer to be used by writing to the SEL bit (DPS.0). The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. ...

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... When the DS89C420 is powered up and has entered its user operating mode, the ROM loader mode can be invoked at any time by forcing RST = and PSEN = 0. It remains in effect until power-down or when the condition (RST = 1 and PSEN = removed ...

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... Separate instructions are used for the option control register. The following sequence can be used to program the flash memory in the parallel programming mode: 1) The DS89C420 is powered up and running at a clock speed between 4MHz and 6MHz. 2) Set RST = and PSEN = 0. 3) Apply the appropriate logic combination to pins P2.6, P2.7, P3.6, and P3.7 to select one of the flash ...

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... ID0 SEL = 0 0 Increment DPTR 1 Decrement DPTR 0 Increment DPTR 1 Decrement DPTR DS89C420 Ultra-High-Speed Microcontroller P3.6 P3.7 OPERATION Mass erase the 16k x 8 program memory, the security block and the bank L L select. The contents of every memory location is returned to FFh Program the 16k program memory ...

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... However, a page mode external memory cycle can be completed system clocks for a page hit and system clocks for a page miss, depending on user selection. The DS89C420 also supports a second page mode operation with a different external bus structure that provides for fast external code fetches but uses 4 system clock cycles for data memory access ...

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Figure 8. External Program Memory Access (Non-Page Mode and CD1:CD0 = 10) Internal Memory Cycles XTAL1 ALE PSEN Port 0 Port 2 Table 5. Data Memory Cycle Stretch Values STRETCH MD2:MD0 CYCLES 000 0 001 1 010 2 011 3 ...

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Figure 9. Non-Page Mode, External Data-Memory Access (Stretch = 0, CD1:CD2 = 10) XTAL1 ALE PSEN RD WR Port 0 A MOVX Port 2 A MOVX Instruction Fetch Figure 10. Non-Page Mode, External Data-Memory Access (Stretch = 1, CD1:CD2 = ...

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... The DS89C420 supports page mode in two external bus structures. The logic value of the page mode select bits in the ACON register determines the external bus structure and the basic memory cycle in the number of system clocks ...

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Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b: PSEN is asserted for both page hit and page miss for a full clock cycle. § § The execution of ...

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Figure 11. Page Mode 1, External Memory Cycle (CD1:CD0 = 10) Internal Memory Cycles XTAL1 ALE PSEN Port 0 Port 2 MSB LSB Page Miss ALE PSEN Port 0 Port 2 MSBAdd ALE PSEN ...

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... Port 2 STRETCH EXTERNAL DATA MEMORY CYCLE IN PAGE MODE The DS89C420 allows software to adjust the speed of external data memory access by stretching the memory bus cycle in page mode operation just like non-page mode operation. The following tables summarize the stretch values and their effects on the external MOVX-memory bus cycle and the control signals’ pulse width in terms of the number of oscillator clocks ...

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Table 9. Page Mode 1, Data Memory Cycle Stretch Values (Pages1:Pages0 = 10) STRETCH MD2:MD0 CYCLES 000 0 001 1 010 2 011 3 100 7 101 8 110 9 111 10 Table 10. Page Mode 2, Data Memory Cycle ...

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Figure 13. Page Mode 1, External Data Memory Access (Pages = 01, Stretch = 10) XTAL1 ALE PSEN Port 0 Inst Inst Port 2 LSB Addr LSB Addr ALE PSEN Port ...

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... INTERRUPTS The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power-fail, are controlled by a series combination of individual enable bits and a global enable (EA) in the interrupt enable register (IE ...

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... Unless marked in Table 11, all these flags must be cleared by software. TIMER/COUNTERS Three 16-bit timers are incorporated in the DS89C420. All three timers can be used as either counters of external events, where 1-to-0 transitions on a port pin are monitored and counted, or timers that count oscillator cycles. Table 12 summarizes the timer functions ...

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Each timer can also be used as a counter of external pulses on the corresponding T0/T1 pin for 1-to-0 transitions. The timer mode (TMOD) register controls the operation mode. Each timer consists of a 16-bit register in ...

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... An on-chip crystal multiplier allows the DS89C420 to operate at two or four times the crystal frequency by setting the 4X/ 2X bit and is enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide-by-1024. ...

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... POR (WDCON.6) is set to logic 1 to indicate a power-on reset has occurred, and can only be cleared by software. When the DS89C420 enters stop mode, the bandgap, reset comparator, and power-fail interrupt comparator are automatically disabled to conserve power, if the BGS (EXIF.0) bit is set to a logic 0. This is the lowest power mode. ...

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WATCHDOG TIMER The watchdog timer functions as the source of both the watchdog interrupt and the watchdog reset. When the clock divider is set to 10b, the interrupt timeout has a default divide ratio of 2 watchdog reset set to ...

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... POWER MANAGEMENT MODE Power management mode offers a software-controllable power-saving scheme by providing a reduced instruction cycle speed, which allows the DS89C420 to continue to operate while using an internally divided version of the clock source to save power. Power management mode is invoked by software setting the clock-divide control bits CD1 and CD0 (PMR ...

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Table 14. Effect of Clock Mode on Timer Operation (in Number of Oscillator Clocks) OSC. CYCLES 4X/2X, CD1, CD0 PER MACHINE CYCLE 100 0.25 000 0.5 x01 1 (reserved) x10 1 (default) x11 1,024 x = don’t care RING OSCILLATOR ...

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... SERIAL I/O The DS89C420 provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1) and has duplicate control functions included in new SFR locations. ...

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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) PKG 40-PIN DIM MIN A — A1 0.015 A2 0.140 b 0.014 c 0.008 D ...

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Note 1: Pin 1 identifier to be located in zone indicated. Note 2: Controlling dimensions are in inches (in ...

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... RST 9 32 P3.0/RXD0 10 DS89C420 31 P3.1/TXD0 11 30 P3.2/INT0 12 29 P3.3/INT1 13 28 P3.4/ P3.5/ P3.6/ P3.7/ XTAL2 18 23 XTAL1 DIP Dallas Semiconductor DS89C420 TQFP V CC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2 ...

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... Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time DESCRIPTION www.maxim-ic.com/errata for details.) © 2003 Maxim Integrated Products · Printed USA ...