C8051F353 Silicon Laboratories Inc, C8051F353 Datasheet - Page 50
![IC 8051 MCU 8K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F353
Manufacturer Part Number
C8051F353
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F353
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Part Number:
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Manufacturer:
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C8051F350/1/2/3
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Bits 7-0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7-0.
This SFR can only be modified when ADC0 is in IDLE mode.
Bits 7-0: ADC0DAC: ADC0 PGA Offset DAC Magnitude.
This SFR can only be modified when ADC0 is in IDLE mode.
DECI7
R/W
R/W
Bit7
Bit7
Figure 5.10. ADC0DECL: ADC0 Decimation Ratio Register Low Byte
This register contains the low byte of the 11-bit ADC Decimation Ratio. The decimation ratio
determines the number of modulator input samples used to generate a single output word
from the ADC.
The ADC0 decimation ratio is defined as:
Decimation Ratio = DECI[10:0] + 1
The corresponding sampling period and output word rate of ADC0 is:
ADC0 Conversion Period = [(DECI[10:0] + 1) * 128] / MDCLK
ADC0 Output Word Rate = MDCLK / [128 * (DECI[10:0] + 1)]
The minimum decimation ratio setting is 20. Any register setting below 19 will automatically
be interpreted as 19.
Important: When using the fast filter, the decimation ratio must be divisible by 8
(DECI[2:0] = 111b).
This register determines the ADC0 Offset DAC Magnitude. The value in the offset DAC is a
signed-magnitude representation. Bit 7 represents the sign value (0 = positive, 1 = nega-
tive), while Bits 6-0 represent the magnitude.
DECI6
R/W
R/W
Bit6
Bit6
Figure 5.11. ADC0DAC: ADC0 Offset DAC Register
DECI5
R/W
R/W
Bit5
Bit5
DECI4
R/W
R/W
Bit4
Bit4
ADC0DAC
Rev. 0.4
DECI3
R/W
R/W
Bit3
Bit3
DECI2
R/W
R/W
Bit2
Bit2
DECI1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
DECI0
R/W
R/W
Bit0
Bit0
0x9A
0xBF
00000000
Reset Value
Reset Value
11111111
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