C8051F353 Silicon Laboratories Inc, C8051F353 Datasheet - Page 113
C8051F353
Manufacturer Part Number
C8051F353
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F353
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
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14.2. Power-Fail Reset /
When a power-down transition or power irregularity causes V
monitor will drive the /RST pin low and hold the CIP-51 in a reset state (see Figure 14.2). When V
returns to a level above V
nal data memory contents are not altered by the power-fail reset, it is impossible to determine if V
dropped below the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be
valid. The V
defined state (enabled/disabled) is not altered by any other reset source. For example, if the V
is disabled by software, and a software reset is performed, the V
reset. To protect the integrity of Flash contents, it is strongly recommended that the V
remain enabled and selected as a reset source if software contains routines which erase or write
Flash memory.
The V
reset source before it is enabled and stabilized may cause a system reset. The procedure for re-enabling
the V
See Figure 14.2 for V
See Table 14.1 for complete electrical characteristics of the V
Bit7:
Bit6:
Bits5-0:
VDMEN
DD
R/W
DD
Bit7
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
monitor and configuring the V
monitor must be enabled before it is selected as a reset source. Selecting the V
Note: This delay should be omitted if software contains routines which erase or write
Flash memory.
VDMEN: V
This bit is turns the V
resets until it is also selected as a reset source in register RSTSRC (Figure 14.4). The V
Monitor must be allowed to stabilize before it is selected as a reset source. Selecting the
V
See Table 14.1 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Reserved. Read = Variable. Write = don’t care.
DD
DD
DD
V
DD
DD
DD
DD
DD
monitor is enabled and selected as a reset source after power-on resets; however its
monitor as a reset source before it has stabilized may generate a system reset.
STAT: V
Bit6
R
STAT Reserved Reserved Reserved Reserved Reserved Reserved
Monitor Disabled.
Monitor Enabled (default).
is at or below the V
is above the V
DD
DD
monitor timing; note that the reset delay is not incurred after a V
DD
RST
Figure 14.3. VDM0CN:
Monitor Enable.
Status.
DD
Bit5
, the CIP-51 will be released from the reset state. Note that even though inter-
DD
R
DD
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
V
monitor (VDMEN bit in VDM0CN = ‘1’).
monitor to stabilize (see Table 14.1 for the V
DD
DD
DD
monitor circuit on/off. The V
Monitor
monitor threshold.
DD
DD
Bit4
R
monitor as a reset source is shown below:
monitor threshold.
DD
Rev. 0.4
Monitor turn-on time.
Bit3
R
V
DD
Monitor Control
DD
Bit2
DD
R
DD
DD
monitor.
DD
to drop below V
Monitor output).
Monitor cannot generate system
monitor will still be disabled after the
C8051F350/1/2/3
Bit1
R
DD
Monitor turn-on time).
SFR Address:
RST
Bit0
R
, the power supply
DD
DD
monitor reset.
0xFF
monitor as a
Reset Value
DD
Variable
DD
monitor
monitor
DD
113
DD
DD
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