C8051F353 Silicon Laboratories Inc, C8051F353 Datasheet - Page 182
![IC 8051 MCU 8K FLASH 28MLP](/photos/6/93/69391/sl-28-mlp_sml.jpg)
C8051F353
Manufacturer Part Number
C8051F353
Description
IC 8051 MCU 8K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F353
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x16b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F353-GM
Manufacturer:
SiliconL
Quantity:
8 050
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C8051F350/1/2/3
21.5. Serial Clock Timing
Four combinations of serial clock phase and polarity can be selected using the clock control bits in the
SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.4) selects between an active-high or active-low
clock. Both master and slave devices must be configured to use the same clock phase and polarity. SPI0
should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships are shown in Figure 21.5.
The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 21.8 controls the master mode serial clock
frequency. This register is ignored when operating in slave mode. When the SPI is configured as a master,
the maximum data transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is
slower. When the SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex
operation is 1/10 the system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave
mode), and the serial input data synchronously with the slave’s system clock. If the master issues SCK,
NSS, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less
than 1/10 the system clock frequency. In the special case where the master only wants to transmit data to
the slave and does not need to receive data from the slave (i.e. half-duplex operation), the SPI slave can
receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided
that the master issues SCK, NSS, and the serial input data synchronously with the slave’s system clock.
21.6. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN
Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate
Register. The four special function registers related to the operation of the SPI0 Bus are described in the
following figures.
182
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
Figure 21.5. Data/Clock Timing Relationship
MSB
Bit 6
Bit 5
Rev. 0.4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
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