C8051F353 Silicon Laboratories Inc, C8051F353 Datasheet
C8051F353
Specifications of C8051F353
Available stocks
Related parts for C8051F353
C8051F353 Summary of contents
Page 1
Analog Peripherals - 24 or 16-Bit ADC • No missing codes • 0.0015% nonlinearity • Programmable conversion rates ksps • 8-Input multiplexer • 128x PGA • Built-in temperature sensor - Two 8-Bit Current Output DACs ...
Page 2
C8051F350/1/2/3 2 Notes Rev. 0.4 ...
Page 3
Table of Contents 1. System Overview.................................................................................................... 13 1.1. CIP-51™ Microcontroller................................................................................... 19 1.1.1. Fully 8051 Compatible Instruction Set...................................................... 19 1.1.2. Improved Throughput ............................................................................... 19 1.1.3. Additional Features .................................................................................. 19 1.2. On-Chip Debug Circuitry................................................................................... 20 1.3. On-Chip Memory............................................................................................... 21 1. ...
Page 4
C8051F350/1/2/3 7. Voltage Reference .................................................................................................. 67 8. Temperature Sensor............................................................................................... 71 9. Comparator0 ........................................................................................................... 73 9.1. Comparator0 Inputs and Outputs...................................................................... 77 10. CIP-51 Microcontroller ........................................................................................... 81 10.1.Instruction Set................................................................................................... 83 10.1.1.Instruction and CPU Timing ..................................................................... 83 10.1.2.MOVX Instruction and Program Memory ................................................. ...
Page 5
Oscillator Drive Circuit...................................................................... 127 17.2.1.Clocking Timers Directly Through the External Oscillator...................... 127 17.2.2.External Crystal Example....................................................................... 127 17.2.3.External RC Example............................................................................. 128 17.2.4.External Capacitor Example................................................................... 128 17.3.Clock Multiplier ............................................................................................... 130 17.4.System Clock Selection.................................................................................. 131 18. Port Input/Output.................................................................................................. 133 18.1.Priority Crossbar Decoder ...
Page 6
C8051F350/1/2/3 21.6.SPI Special Function Registers ...................................................................... 182 22. Timers.................................................................................................................... 191 22.1.Timer 0 and Timer 1 ....................................................................................... 191 22.1.1.Mode 0: 13-bit Counter/Timer ................................................................ 191 22.1.2.Mode 1: 16-bit Counter/Timer ................................................................ 192 22.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload...................................... 193 22.1.4.Mode 3: Two 8-bit ...
Page 7
... Table 1.1. Product Selection Guide ........................................................................ 14 Figure 1.1. C8051F350 Block Diagram .................................................................... 15 Figure 1.2. C8051F351 Block Diagram .................................................................... 16 Figure 1.3. C8051F352 Block Diagram .................................................................... 17 Figure 1.4. C8051F353 Block Diagram .................................................................... 18 Figure 1.5. Development/In-System Debug Diagram............................................... 20 Figure 1.6. Memory Map .......................................................................................... 21 Figure 1.7. ADC0 Block Diagram ............................................................................. 22 Figure 1.8. IDAC Block Diagram .............................................................................. 23 Figure 1 ...
Page 8
C8051F350/1/2/3 Figure 5.14. ADC0COH: ADC0 Offset Calibration Register High Byte .................... 53 Figure 5.15. ADC0COM: ADC0 Offset Calibration Register Middle Byte................. 53 Figure 5.16. ADC0COL: ADC0 Offset Calibration Register Low Byte...................... 53 Figure 5.17. ADC0CGH: ADC0 Gain Calibration Register High ...
Page 9
Figure 10.2. SP: Stack Pointer ................................................................................. 87 Figure 10.3. DPL: Data Pointer Low Byte................................................................. 87 Figure 10.4. DPH: Data Pointer High Byte ............................................................... 87 Figure 10.5. PSW: Program Status Word................................................................. 88 Figure 10.6. ACC: Accumulator................................................................................ 89 Figure 10. ...
Page 10
C8051F350/1/2/3 Figure 18.3. Crossbar Priority Decoder with No Pins Skipped ............................... 135 Figure 18.4. Crossbar Priority Decoder with Crystal Pins Skipped ........................ 136 Figure 18.5. XBR0: Port I/O Crossbar Register 0................................................... 138 Figure 18.6. XBR1: Port I/O Crossbar Register 1................................................... ...
Page 11
Table 20.6. Timer Settings for Standard Baud Rates Using an External Oscillator 176 21. Serial Peripheral Interface (SPI0) ....................................................................... 177 Figure 21.1. SPI Block Diagram ............................................................................. 177 Figure 21.2. Multiple-Master Mode Connection Diagram ....................................... 180 Figure 21.3. 3-Wire Single Master ...
Page 12
C8051F350/1/2/3 Figure 23.3. PCA Interrupt Block Diagram ............................................................. 209 Table 23.2. PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 209 Figure 23.4. PCA Capture Mode Diagram.............................................................. 210 Figure 23.5. PCA Software Timer Mode Diagram .................................................. 211 Figure 23.6. PCA High ...
Page 13
System Overview C8051F350/1/2/3 devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, non-intrusive debug ...
Page 14
... C8051F350/1/2/3 Table 1.1. Product Selection Guide C8051F350 768 C8051F351 768 C8051F352 768 C8051F353 768 Rev. 0.4 LQFP-32 MLP-28 LQFP-32 MLP-28 ...
Page 15
Digital Power VDD GND Analog AV+ Power C2D AGND Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit 24.5MHz 2% Clock Internal Multiplier Oscillator VREF+ VREF- AIN0 AIN1 Offset AIN2 A + AIN3 Buffer PGA M + AIN4 ...
Page 16
C8051F350/1/2/3 Digital Power VDD GND Analog AV+ Power C2D AGND Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit 24.5MHz 2% Clock Internal Multiplier Oscillator VREF+ VREF- AIN0 AIN1 AIN2 A + AIN3 Buffer M + AIN4 U ...
Page 17
Digital Power VDD GND Analog AV+ Power C2D AGND Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator XTAL2 Circuit 24.5MHz 2% Clock Internal Multiplier Oscillator VREF+ VREF- AIN0 AIN1 Offset AIN2 A + AIN3 Buffer PGA M + AIN4 ...
Page 18
... Circuit x2 24.5MHz 2% Internal Oscillator VREF+ VREF- AIN0 AIN1 AIN2 A + AIN3 Buffer M + AIN4 U X AIN5 AIN6 Temp Sensor AIN7 Figure 1.4. C8051F353 Block Diagram 18 8kbyte 8 FLASH 0 256 byte Port 0 Reset 5 SRAM Latch 1 512 byte UART XRAM Timer SFR Bus o 3-Chnl PCA/ System ...
Page 19
CIP-51™ Microcontroller 1.1.1. Fully 8051 Compatible Instruction Set The C8051F35x devices use Silicon Labs’ proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop software. ...
Page 20
C8051F350/1/2/3 1.2. On-Chip Debug Circuitry The C8051F350/1/2/3 devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non- intrusive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and ...
Page 21
On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct ...
Page 22
C8051F350/1/2/3 1. 16-Bit Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) Sigma- Delta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation fil- ters can be programmed for ...
Page 23
Two 8-bit Current-Mode DACs The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and 2 mA. A ...
Page 24
C8051F350/1/2/3 1.6. Programmable Comparator C8051F350/1/2/3 devices include a software-configurable voltage comparator with an input multiplexer. The Comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or ...
Page 25
Port Input/Output C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be config- ured ...
Page 26
C8051F350/1/2/3 1.9. Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and three 16-bit capture/compare modules. The counter/timer is ...
Page 27
Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Pin (except V , AV+, and DD Port I/O) with respect to DGND Voltage on any Port I/O Pin or /RST ...
Page 28
C8051F350/1/2/3 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics -40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter Analog Supply Voltage (Note 1) Analog Supply Current Internal REF, ADC, IDACs, Comparators all active Analog ...
Page 29
Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F350/1/2/3 Pin Numbers Name ‘F350 ‘F351 ‘F352 ‘F353 DGND AGND 9 5 /RST 12 8 C2CK P2. C2D ...
Page 30
C8051F350/1/2/3 Table 4.1. Pin Definitions for the C8051F350/1/2/3 (Continued) Pin Numbers Name ‘F350 ‘F351 ‘F352 ‘F353 P0. CNVSTR P0 P1. AIN0.4 P1. AIN0.5 P1. AIN0.6 P1. AIN0.7 P1.4 ...
Page 31
Table 4.1. Pin Definitions for the C8051F350/1/2/3 (Continued) Pin Numbers Name Type ‘F350 ‘F351 ‘F352 ‘F353 AIN0 AIN0 AIN0 AIN0 AIN0 ...
Page 32
C8051F350/1/2/3 AIN0 AIN0.1 3 AIN0.2 4 AIN0.3 AIN0.4 5 AIN0 AIN0.6 8 AIN0.7 Figure 4.1. LQFP-32 Pinout Diagram (Top View) 32 C8051F350 C8051F352 Top View Rev. 0.4 24 P1.1 23 P1.0 22 DGND 21 VDD 20 ...
Page 33
... GND AIN0.0 1 AIN0.1 2 AIN0.2 3 AIN0.3 4 AGND 5 AV+ 6 P2.0 / C2D 7 Figure 4.2. MLP-28 Pinout Diagram (Top View) C8051F350/1/2/3 C8051F351 C8051F353 Top View GND Rev. 0.4 21 P1.2 / AIN0.6 20 P1.1 / AIN0.5 19 P1.0 / AIN0.4 18 DGND 17 VDD 16 P0.7 15 P0.6 33 ...
Page 34
C8051F350/1/2 PIN 1 IDENTIFIER Figure 4.3. LQFP-32 Package Diagram 34 Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. ...
Page 35
Bottom View DETAIL Side View e DETAIL Figure 4.4. MLP-28 Package Drawing C8051F350/1/2/3 Table 4.2. MLP-28 Package Dimensions MIN 15 A 0.80 ...
Page 36
C8051F350/1/2/3 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.5. Typical MLP-28 Landing Diagram 36 Top View E2 E Rev. 0.4 0.85 mm ...
Page 37
L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.6. Typical MLP-28 Solder Paste Diagram C8051F350/1/2/3 Top View 0.60 mm 0.30 mm 0. ...
Page 38
C8051F350/1/2/3 38 Rev. 0.4 ...
Page 39
Analog to Digital Converter (ADC0) The C8051F350/1/2/3 include a fully-differential, 24-bit (C8051F350/1) or 16-bit (C8051F352/3) Sigma- Delta Analog to Digital Converter (ADC) with on-chip calibration capabiliites. Two separate decimation fil- ters can be programmed for throughputs ...
Page 40
C8051F350/1/2/3 5.1. Configuration ADC0 is enabled by setting the AD0EN bit in register ADC0MD (Figure 5.7) to ‘1’. When the ADC is dis- abled placed in a low-power shutdown mode with all clocks turned off, to minimize unnecessary ...
Page 41
AIN+ Channel AIN- Channel Figure 5.2. ADC0 Buffer Control 5.1.3. Modulator Clock The ADC0CLK register (Figure 5.8) holds the Modulator Clock (MDCLK) divisor value. The modulator clock determines the switching frequency for the ADC sampling capacitors. Optimal performance will be ...
Page 42
C8051F350/1/2/3 5.2. Calibrating the ADC ADC0 can be calibrated in-system for both gain and offset, using internal or system calibration modes. To ensure calibration accuracy, offset calibrations must be performed prior to gain calibrations not neces- sary to ...
Page 43
ADC0CGH, ADC0CGM, and ADC0CGL registers. The mapping of the gain register is shown in Figure 5.4. The offset calibration value adjusts the zero point of the ADC’s transfer function stored as a two’s complement, 24-bit number. An offset ...
Page 44
C8051F350/1/2/3 5.3. Performing Conversions The ADC offers two conversion modes: Single Conversion, and Continuous Conversion. In single conver- sion mode, a single conversion result is produced for each of the filters (SINC3 and Fast). In continuous conversion mode, the ADC ...
Page 45
Table 5.1. ADC0 Unipolar Output Word Coding (AD0POL = 0) Input Voltage† (AIN+ - AIN-) 24-bit Output Word (C8051F350/1) 16-bit Output Word (C8051F352/3) VREF - 1 LSB VREF / 2 +1 LSB 0 †Input Voltage is voltage at ADC inputs ...
Page 46
C8051F350/1/2/3 exists between AIN+ and AIN- when the burnout current sources are enabled, the ADC will read a value near zero. The burnout current sources should be disabled during normal ADC measurements. Figure 5.5. ADC0CN: ADC0 Control Register R R ...
Page 47
Figure 5.6. ADC0CF: ADC0 Configuration Register Bit7 Bit6 Bit5 Bits 7-5: Unused: Read = 000b, Write = don’t care. Bit 4: AD0ISEL: ADC0 Interrupt Source Select. This bit selects which filter completion will set ...
Page 48
C8051F350/1/2/3 Figure 5.7. ADC0MD: ADC0 Mode Register R/W R R/W AD0EN - Reserved Reserved Bit7 Bit6 Bit5 Bit 7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC is in low-power shutdown. 1: ADC0 Enabled. ADC is active and ready to ...
Page 49
Figure 5.8. ADC0CLK: ADC0 Modulator Clock Divisor R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC0CLK: ADC0 Modulator Clock Divisor. This register establishes the Modulator Clock (MDCLK), by dividing down the system clock (SYSCLK). The input signal is sampled by ...
Page 50
C8051F350/1/2/3 Figure 5.10. ADC0DECL: ADC0 Decimation Ratio Register Low Byte R/W R/W R/W DECI7 DECI6 DECI5 Bit7 Bit6 Bit5 Bits 7-0: DECI[7:0]: ADC0 Decimation Ratio Register, Bits 7-0. This register contains the low byte of the 11-bit ADC Decimation Ratio. ...
Page 51
Figure 5.12. ADC0BUF: ADC0 Input Buffer Control Register R/W R/W R/W AD0BPHE AD0BPLE AD0BPS Bit7 Bit6 Bit5 Bit 7: AD0BPHE: Positive Channel High Buffer Enable. 0: Positive Channel High Input Buffer Disabled. 1: Positive Channel High Input Buffer Enabled. Bit ...
Page 52
C8051F350/1/2/3 Figure 5.13. ADC0STA: ADC0 Status Register R R R/W AD0BUSY AD0CBSY AD0INT Bit7 Bit6 Bit5 Bit 7: AD0BUSY: ADC0 Conversion In-Progress Flag. 0: ADC0 is not performing conversions. 1: ADC0 conversion in progress. Bit 6: AD0CBSY: ADC0 Calibration In-Progress ...
Page 53
Figure 5.14. ADC0COH: ADC0 Offset Calibration Register High Byte R/W R/W R/W OCAL23 OCAL22 OCAL21 Bit7 Bit6 Bit5 Bits 7-0: OCAL[23:16]: ADC0 Offset Calibration Register High Byte. This register contains the high byte of the 24-bit ADC Offset Calibration Value. ...
Page 54
C8051F350/1/2/3 Figure 5.17. ADC0CGH: ADC0 Gain Calibration Register High Byte R/W R/W R/W GCAL23 GCAL22 GCAL21 Bit7 Bit6 Bit5 Bits 7-0: GCAL[23:16]: ADC0 Gain Calibration Register High Byte. This register contains the high byte of the 24-bit ADC Gain Calibration ...
Page 55
Figure 5.20. ADC0H: ADC0 Conversion Register (SINC3 Filter) High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC0H: ADC0 Conversion Register (SINC3 Filter) High Byte. C8051F350/1: This register contains bits 23-16 of the 24-bit ADC SINC3 filter conversion result. ...
Page 56
C8051F350/1/2/3 Figure 5.23. ADC0FH: ADC0 Conversion Register (Fast Filter) High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: ADC0FH: ADC0 Conversion Register (Fast Filter) High Byte. C8051F350/1: This register contains bits 23-16 of the 24-bit ADC fast filter conversion ...
Page 57
Analog Multiplexer ADC0 includes analog multiplexer circuitry with independent selection capability for the AIN+ and AIN- inputs. Each input can be connected to one of ten possible input sources: AIN0.0 though AIN0.7, AGND, or the on-chip temperature sensor circuitry ...
Page 58
C8051F350/1/2/3 Figure 5.27. ADC0MUX: ADC0 Analog Multiplexer Control Register R/W R/W R/W AD0PSEL Bit7 Bit6 Bit5 Bits 7-4: AD0PSEL: ADC0 Positive Multiplexer Channel Select. 0000 = AIN0.0 0001 = AIN0.1 0010 = AIN0.2 0011 = AIN0.3 0100 = AIN0.4 0101 ...
Page 59
Table 5.3. ADC0 Electrical Characteristics V = AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1, MDCLK = 2.4576 MHz, DD Decimation Ratio = 1920, -40 to +85 °C unless otherwise noted. Parameter 24-bit ADC (C8051F350/1) ...
Page 60
C8051F350/1/2/3 Table 5.3. ADC0 Electrical Characteristics (Continued AV+ = 3.0 V, VREF = 2.5 V External, PGA Gain = 1, MDCLK = 2.4576 MHz, DD Decimation Ratio = 1920, -40 to +85 °C unless otherwise noted. Parameter Power ...
Page 61
Current Mode DACS (IDA0 and IDA1) The C8051F350/1/2/3 devices include two 8-bit current-mode Digital-to-Analog Converters (IDACs). The maximum current output of the IDACs can be adjusted for four different current settings; 0.25 mA, 0.5 mA, 1 mA, and ...
Page 62
C8051F350/1/2/3 6.1. IDAC Output Scheduling A flexible output update mechanism allows for seamless full-scale changes and supports jitter-free updates for waveform generation. Three update modes are provided, allowing IDAC output updates on a write to the IDAC’s data register, on ...
Page 63
Figure 6.3. IDA0CN: IDA0 Control Register R/W R/W R/W IDA0EN IDA0CM Bit7 Bit6 Bit5 Bit 7: IDA0EN: IDA0 Enable. 0: IDA0 Disabled. 1: IDA0 Enabled. Bits 6-4: IDA0CM[2:0]: IDA0 Update Source Select bits. 000: DAC output updates on Timer 0 ...
Page 64
C8051F350/1/2/3 Figure 6.5. IDA1CN: IDA1 Control Register R/W R/W R/W IDA1EN IDA1CM Bit7 Bit6 Bit5 Bit 7: IDA1EN: IDA1 Enable. 0: IDA1 Disabled. 1: IDA1 Enabled. Bits 6-4: IDA1CM[2:0]: IDA1 Update Source Select bits. 000: DAC output updates on Timer ...
Page 65
IDAC External Pin Connections The IDA0 output is connected to P1.6, and the IDA1 output is connected to P1.7. When the enable bit for an IDAC (IDAnEN) is set to ‘0’, the IDAC output behaves as a normal GPIO ...
Page 66
C8051F350/1/2/3 . Table 6.1. IDAC Electrical Characteristics -40 to +85° 3.0 V Full-scale output current set unless otherwise specified. DD Parameter Static Performance Resolution Integral Nonlinearity Differential Nonlinearity Guaranteed Monotonic Output Compliance Range Output Noise ...
Page 67
Voltage Reference There are two voltage reference options for the C8051F350/1/2/3 ADCs: the internal 2.5 V reference volt- age external reference voltage (see Figure 7.1). The AD0VREF bit in the ADC0CF register selects the reference source. The ...
Page 68
C8051F350/1/2/3 Figure 7.2. REF0CN: Reference Control Register Bit7 Bit6 Bit5 NOTE: Modification of this register is not necessary in most applications. The appropriate circuitry is enabled when it is needed by a peripheral. Bits7-2: ...
Page 69
Table 7.1. Voltage Reference Electrical Characteristics V = 3.0 V; -40 to +85 °C unless otherwise specified DD Parameter Internal Reference Output Voltage 25°C ambient VREF Short-Circuit Current To AGND To AV+ VREF Temperature Coefficient Load Regulation Load = 0 ...
Page 70
C8051F350/1/2/3 70 Rev. 0.4 ...
Page 71
Temperature Sensor The temperature sensor system consists of two diodes with different temperature properties and two con- stant current sources. The two channels are connected to the ADC inputs internally, using the ADC’s ana- log multiplexer. The temperature sensor ...
Page 72
C8051F350/1/2/3 -50 Figure 8.2. Single Channel Transfer Function -50 Figure 8.3. Differential Transfer Function (Slope x Temp ) + Offset TEMP C Temp = (V - Offset) / Slope C TEMP Offset ( Celsius) Slope ...
Page 73
Comparator0 C8051F350/1/2/3 devices include an on-chip programmable voltage comparator, Comparator0, shown in Figure 9.1. The Comparator offers programmable response time and hysteresis and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0), or ...
Page 74
C8051F350/1/2/3 CP0+ VIN+ + CP0 CP0- _ VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN OUTPUT V OL Positive Hysteresis Disabled Figure 9.2. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its ...
Page 75
Figure 9.3. CPT0CN: Comparator0 Control Register R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: Voltage ...
Page 76
C8051F350/1/2/3 Figure 9.4. CPT0MD: Comparator0 Mode Selection Register CP0RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 Rising-edge interrupt disabled. 1: Comparator0 Rising-edge ...
Page 77
Comparator0 Inputs and Outputs Figure 9.5 shows the external pin connections for the comparator. The positive and negative inputs to the comparator can each be routed to one of eight different pins using the comparator mux. Comparator out- puts ...
Page 78
C8051F350/1/2/3 Figure 9.6. CPT0MX: Comparator0 MUX Selection Register R/W R/W R/W CMX0N3 CMX0N2 CMX0N1 CMX0N0 CMX0P3 CMX0P2 CMX0P1 Bit7 Bit6 Bit5 Bits7-4: CMX0N2-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is used as the Comparator0 negative ...
Page 79
Table 9.1. Comparator Electrical Characteristics VDD = 3.0 V, -40 to +85 °C unless otherwise noted. Parameter Response Time: CP0+ - CP0- = 100 mV † Mode 0, Vcm = 1.5 V CP0+ - CP0- = -100 mV Response Time: ...
Page 80
C8051F350/1/2/3 80 Rev. 0.4 ...
Page 81
CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set. Standard 803x/805x assemblers and compilers can be used to develop soft- ware. The C8051F35x family has a superset ...
Page 82
C8051F350/1/2/3 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...
Page 83
Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary ...
Page 84
C8051F350/1/2/3 Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide Decimal adjust A ANL A, Rn AND ...
Page 85
Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic MOV @Ri, direct Move direct byte to indirect RAM MOV @Ri, #data Move immediate to indirect RAM MOV DPTR, #data16 Load DPTR with 16-bit constant MOVC A, @A+DPTR Move code byte relative ...
Page 86
C8051F350/1/2/3 Table 10.1. CIP-51 Instruction Set Summary (Continued) Mnemonic CJNE A, #data, rel Compare immediate to A and jump if not equal Compare immediate to Register and jump if not CJNE Rn, #data, rel equal Compare immediate to indirect and ...
Page 87
Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic l. Future product versions may use these bits to implement new features in which case ...
Page 88
C8051F350/1/2/3 Figure 10.5. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction ...
Page 89
Figure 10.6. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7-0: ACC: Accumulator. This register is the accumulator for arithmetic operations. Figure 10. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7-0: B: ...
Page 90
C8051F350/1/2/3 10.3. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all interrupts ...
Page 91
Figure 10.8. PCON: Power Control R/W R/W R Bit7 Bit6 Bit5 Bits7-3: Reserved. Bit1: STOP: STOP Mode Select. Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’. ...
Page 92
C8051F350/1/2/3 92 Rev. 0.4 ...
Page 93
Memory Organization and SFRs The memory organization of the C8051F350/1/2/3 is similar to that of a standard 8051. There are two sep- arate memory spaces: program memory and data memory. Program and data memory share the same address space ...
Page 94
C8051F350/1/2/3 11.2. Data Memory The C8051F350/1/2/3 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either ...
Page 95
Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...
Page 96
C8051F350/1/2/3 Table 11.2. Special Function Registers SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description ACC 0xE0 Accumulator ADC0BUF 0xBD ADC0 Buffer Control ADC0CF 0xFB ADC0 Configuration ADC0CGH 0xAD ADC0 Gain Calibration High ADC0CGL ...
Page 97
Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description IT01CF 0xE4 INT0/INT1 Configuration OSCICL 0xB3 Internal Oscillator Calibration OSCICN 0xB2 Internal Oscillator Control OSCXCN 0xB1 External Oscillator Control ...
Page 98
C8051F350/1/2/3 Table 11.2. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved Register Address Description TH1 0x8D Timer/Counter 1 High TL0 0x8A Timer/Counter 0 Low TL1 0x8B Timer/Counter 1 Low TMOD 0x89 Timer/Counter ...
Page 99
Interrupt Handler The C8051F35x family includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. The allocation of interrupt sources between on-chip peripherals and external input pins varies according to the specific version ...
Page 100
C8051F350/1/2/3 is made to service the pending interrupt. Therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) occurs when the CPU is performing an RETI ...
Page 101
Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral ...
Page 102
C8051F350/1/2/3 Figure 12.2. IP: Interrupt Priority R R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit 7: UNUSED. Read = 1, Write = don't care. Bit 6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority ...
Page 103
Figure 12.3. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 Reserved ECP0 Bit7 Bit6 Bit5 Bit 7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable ...
Page 104
C8051F350/1/2/3 Figure 12.4. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 Reserved PCP0 Bit7 Bit6 Bit5 Bit 7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set ...
Page 105
External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...
Page 106
C8051F350/1/2/3 Figure 12.5. IT01CF: INT0/INT1 Configuration Register R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 22.4 for INT0/1 edge- or level-sensitive interrupt selection. Bit 7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: ...
Page 107
C8051F350/1/2/3 Rev. 0.4 107 ...
Page 108
C8051F350/1/2/3 108 Rev. 0.4 ...
Page 109
Prefetch Engine The C8051F350/1/2/3 family of devices incorporate a 2-byte prefetch engine. Because the access time of the Flash memory is 40 ns, and the minimum instruction time is 20 ns, the prefetch engine is necessary for full-speed code ...
Page 110
C8051F350/1/2/3 110 Rev. 0.4 ...
Page 111
Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
Page 112
C8051F350/1/2/3 14.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until delay occurs before the device is released from reset; the delay decreases as the ...
Page 113
Power-Fail Reset / V DD When a power-down transition or power irregularity causes V monitor will drive the /RST pin low and hold the CIP- reset state (see Figure 14.2). When V returns to a level above ...
Page 114
C8051F350/1/2/3 14.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of ...
Page 115
Figure 14.4. RSTSRC: Reset Source Register R R R/W - FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bit6: FERROR: Flash Error Indicator. 0: Source of last reset was not a Flash read/write/erase error. ...
Page 116
C8051F350/1/2/3 Table 14.1. Reset Electrical Characteristics -40 to +85 °C unless otherwise specified. Parameter I /RST Output Low Voltage OL /RST Input High Voltage /RST Input Low Voltage /RST Input Pullup Current /RST = 0 POR Threshold (V ...
Page 117
Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system through the C2 interface or by software using the MOVX instruction. Once cleared to logic 0, a ...
Page 118
C8051F350/1/2/3 15.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time groups of two. The FLBWE bit in register PFE0CN (Figure 13.1) controls whether a single byte or a block of two ...
Page 119
Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...
Page 120
C8051F350/1/2/3 Locked when any other Flash pages are locked Access limit set according to the Flash security lock byte Figure 15.1. Flash Memory Map Figure 15.2. PSCTL: Program Store R/W Control Bit7 Bit6 Bit5 ...
Page 121
Figure 15.3. FLKEY: Flash Lock and Key Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: FLKEY: Flash Lock and Key Register Write: This register provides a lock and key function for Flash erasures and writes. Flash writes and erases are ...
Page 122
C8051F350/1/2/3 Table 15.1. Flash Electrical Characteristics V = 2.7 to 3.6 V; -40 to +85 ºC unless otherwise specified DD Parameter Flash Size C8051F350/1/2/3 Endurance Erase Cycle Time 50 MHz System Clock Write Cycle Time 50 MHz System Clock † ...
Page 123
External RAM The C8051F350/1/2/3 devices include 512 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX ...
Page 124
C8051F350/1/2/3 124 Rev. 0.4 ...
Page 125
Oscillators C8051F350/1/2/3 devices include a programmable internal oscillator, an external oscillator drive circuit, and a clock multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 17.1. The system clock ...
Page 126
C8051F350/1/2/3 Figure 17.2. OSCICN: Internal Oscillator Control Register R IOSCEN IFRDY - Bit7 Bit6 Bit5 Bit7: IOSCEN: Internal Oscillator Enable Bit. 0: Internal Oscillator Disabled. 1: Internal Oscillator Enabled. Bit6: IFRDY: Internal Oscillator Frequency Ready Flag. 0: Internal ...
Page 127
External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator must ...
Page 128
C8051F350/1/2/3 17.2.3. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 17.1, Option 2. The capacitor should be no greater than 100 pF; ...
Page 129
Figure 17.4. OSCXCN: External Oscillator Control Register R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal ...
Page 130
C8051F350/1/2/3 17.3. Clock Multiplier The Clock Multiplier generates an output clock which is 4 times the input clock frequency. The Clock Multi- plier’s input can be selected from the external oscillator, or 1/2 the internal or external oscillators. This pro- ...
Page 131
System Clock Selection The internal oscillator requires little start-up time and may be selected as the system clock immediately fol- lowing the OSCICN write that enables the internal oscillator. External crystals and ceramic resonators typ- ically require a start-up ...
Page 132
C8051F350/1/2/3 132 Rev. 0.4 ...
Page 133
Port Input/Output Digital and analog resources are available through 17 I/O pins. Port pins are organized as two byte-wide Ports and one 1-bit Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input/output; ...
Page 134
C8051F350/1/2/3 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT Analog Select ANALOG INPUT PORT-INPUT Figure 18.2. Port I/O Cell Block Diagram 134 VDD VDD (WEAK) GND Rev. 0.4 PORT PAD ...
Page 135
Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 18.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...
Page 136
C8051F350/1/2/3 SF Signals x1 x2 PIN I TX0 RX0 CP0A CP0 SCK MISO MOSI NSS* SDA SCL SYSCLK CEX0 CEX1 CEX2 ECI P0SKIP[7:0] Port pin potentially assignable to peripheral SF ...
Page 137
Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or ...
Page 138
C8051F350/1/2/3 Figure 18.5. XBR0: Port I/O Crossbar Register R CP0AE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP0AE: Comparator0 Asynchronous Output Enable 0: Asynchronous CP0 unavailable at Port pin. ...
Page 139
Figure 18.6. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pull-up Disable. 0: Weak Pull-ups enabled (except for Ports whose I/O are configured as analog input). 1: Weak ...
Page 140
C8051F350/1/2/3 18.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports P0-P2 are accessed through corresponding special function registers (SFRs) that are ...
Page 141
Figure 18.7. P0: Port0 Register R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7-0: P0.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P0MDOUT.n bit ...
Page 142
C8051F350/1/2/3 Figure 18.9. P0MDOUT: Port0 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding ...
Page 143
Figure 18.11. P1: Port1 Register R/W R/W R/W P0.7 P0.6 P0.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n bit ...
Page 144
C8051F350/1/2/3 Figure 18.13. P1MDOUT: Port1 Output Mode Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding ...
Page 145
Figure 18.15. P2: Port2 Register Bit7 Bit6 Bit5 Bits7-1: Unused. Read = 0000000b. Write = don’t care. Bit0: P2.0 Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: ...
Page 146
C8051F350/1/2/3 Table 18.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, -40 to +85 °C unless otherwise specified DD Parameters I = -3mA, Port I/O push-pull -10µA, Port I/O push-pull Output High Voltage OH ...
Page 147
SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system ...
Page 148
C8051F350/1/2/3 19.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: 1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. 2. The I2C-Bus Specification -- Version 2.0, Philips ...
Page 149
SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both ...
Page 150
C8051F350/1/2/3 19.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave ...
Page 151
Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con- trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent ...
Page 152
C8051F350/1/2/3 19.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...
Page 153
Figure 19.4 shows the typical SCL generation described by Equation 19.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by ...
Page 154
C8051F350/1/2/3 Figure 19.5. SMB0CF: SMBus Clock/Configuration Register R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus ...
Page 155
SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see Figure 19.6). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump ...
Page 156
C8051F350/1/2/3 Figure 19.6. SMB0CN: SMBus Control Register R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...
Page 157
Table 19.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When: • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed by ...
Page 158
C8051F350/1/2/3 19.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
Page 159
SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
Page 160
C8051F350/1/2/3 19.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...
Page 161
Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...
Page 162
C8051F350/1/2/3 19.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...
Page 163
SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...
Page 164
C8051F350/1/2/3 Table 19.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A master data byte was received; ACK requested. 1000 slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ...
Page 165
Table 19.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave address was received; ACK requested Lost arbitration as master; slave 0010 address received; ACK requested Lost arbitration while attempting a 0010 ...
Page 166
C8051F350/1/2/3 166 Rev. 0.4 ...
Page 167
UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “20.1. ...
Page 168
C8051F350/1/2/3 20.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
Page 169
Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown below. Figure 20.3. UART Interconnect Diagram 20.2.1. 8-Bit UART 8-Bit UART ...
Page 170
C8051F350/1/2/3 20.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...
Page 171
Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...
Page 172
C8051F350/1/2/3 Figure 20.7. SCON0: Serial Port 0 Control Register R/W R R/W S0MODE - MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: ...
Page 173
Figure 20.8. SBUF0: Serial (UART0) Port Data Buffer Register R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...
Page 174
C8051F350/1/2/3 Table 20.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Frequency: 24.5 MHz Target Baud Rate Baud Rate % Error (bps) 230400 -0.32% 115200 -0.32% 57600 0.15% 28800 -0.32% 14400 0.15% 9600 -0.32% 2400 -0.32% 1200 0.15% ...
Page 175
Table 20.3. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 22.1184 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 ...
Page 176
C8051F350/1/2/3 Table 20.5. Timer Settings for Standard Baud Rates Using an External Oscillator Frequency: 11.0592 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% ...
Page 177
Serial Peripheral Interface (SPI0) The Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple mas- ters and ...
Page 178
C8051F350/1/2/3 21.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 21.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
Page 179
SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...
Page 180
C8051F350/1/2/3 Master Device 1 Figure 21.2. Multiple-Master Mode Connection Diagram Master Device Figure 21.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Master Device GPIO Figure 21.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection 180 NSS GPIO ...
Page 181
SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by ...
Page 182
C8051F350/1/2/3 21.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to ...
Page 183
Figure 21.6. SPI0CFG: SPI0 Configuration Register R R/W R/W SPIBSY MSTEN CKPHA Bit7 Bit6 Bit5 Bit 7: SPIBSY: SPI Busy (read only). This bit is set to logic 1 when a SPI transfer is in progress (Master or Slave Mode). ...
Page 184
C8051F350/1/2/3 Figure 21.7. SPI0CN: SPI0 Control Register R/W R/W R/W SPIF WCOL MODF Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts ...
Page 185
Figure 21.8. SPI0CKR: SPI0 Clock Rate Register R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master mode ...
Page 186
C8051F350/1/2/3 Figure 21.9. SPI0DAT: SPI0 Data Register R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: SPI0DAT: SPI0 Transmit and Receive Data. The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT places the data into ...
Page 187
SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.10. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...
Page 188
C8051F350/1/2/3 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 21.12. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...
Page 189
Table 21.1. SPI Slave Timing Parameters Parameter † Master Mode Timing (See Figure 21.10 and Figure 21.11) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Sample Edge MIS T SCK Sample Edge to ...
Page 190
C8051F350/1/2/3 190 Rev. 0.4 ...
Page 191
Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with other device peripherals or for general purpose use. These timers can be ...
Page 192
C8051F350/1/2/3 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “18.1. Priority Crossbar Decoder” on page 135 ...
Page 193
Mode 2: 8-bit Counter/Timer with Auto-Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. TL0 holds the count and TH0 holds the reload value. When the counter ...
Page 194
C8051F350/1/2/3 22.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in ...
Page 195
Figure 22.4. TCON: Timer Control Register R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared ...
Page 196
C8051F350/1/2/3 Figure 22.5. TMOD: Timer Mode Register R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only ...
Page 197
Figure 22.6. CKCON: Clock Control Register R/W R/W R/W T3MH T3ML T2MH Bit7 Bit6 Bit5 Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured ...
Page 198
C8051F350/1/2/3 Figure 22.7. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. Figure 22.8. TL1: Timer 1 Low Byte ...
Page 199
Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...
Page 200
C8051F350/1/2/3 22.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 22.12. TMR2RLL holds the reload value for TMR2L; ...