MC68HC908JB16JDW Freescale Semiconductor, MC68HC908JB16JDW Datasheet - Page 80
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MC68HC908JB16JDW
Manufacturer Part Number
MC68HC908JB16JDW
Description
IC MCU 16K FLASH 6MHZ USB 20SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB16DWE.pdf
(332 pages)
Specifications of MC68HC908JB16JDW
Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
SCI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908JB16JDWE
Manufacturer:
FREESCALE
Quantity:
20 000
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Central Processor Unit (CPU)
6.4.5 Condition Code Register
Technical Data
80
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
V — Overflow Flag
H — Half-Carry Flag
Reset:
Read:
Write:
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or add-
with-carry (ADC) operation. The half-carry flag is required for binary-
coded decimal (BCD) arithmetic operations. The DAA instruction
uses the states of the H and C flags to determine the appropriate
correction factor.
1 = Overflow
0 = No overflow
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
X = Indeterminate
Bit 7
V
X
Central Processor Unit (CPU)
Figure 6-6. Condition Code Register (CCR)
6
1
1
5
1
1
H
4
X
3
1
I
MC68HC908JB16
Freescale Semiconductor
N
2
X
Z
X
1
—
Rev. 1.1
Bit 0
C
X
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