MC68HC908JB16JDW Freescale Semiconductor, MC68HC908JB16JDW Datasheet - Page 215
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MC68HC908JB16JDW
Manufacturer Part Number
MC68HC908JB16JDW
Description
IC MCU 16K FLASH 6MHZ USB 20SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB16DWE.pdf
(332 pages)
Specifications of MC68HC908JB16JDW
Core Processor
HC08
Core Size
8-Bit
Speed
6MHz
Connectivity
SCI, USB
Peripherals
LED, LVD, POR, PWM
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC908JB16JDWE
Manufacturer:
FREESCALE
Quantity:
20 000
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12.5.2.1 Character Length
12.5.2.2 Character Transmission
MC68HC908JB16
Freescale Semiconductor
—
Rev. 1.1
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCC1) determines character length.
When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3) is
the ninth bit (bit 8).
During an SCI transmission, the transmit shift register shifts a character
out to the TxD pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register. To initiate
an SCI transmission:
At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.
When the transmit shift register is not transmitting a character, the TxD
pin goes to the idle condition, logic 1. If at any time software clears the
ENSCI bit in SCI control register 1 (SCC1), the transmitter and receiver
relinquish control of the port pin.
1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)
2. Enable the transmitter by writing a logic 1 to the transmitter enable
3. Clear the SCI transmitter empty bit by first reading SCI status
4. Repeat step 3 for each subsequent transmission.
Serial Communications Interface Module (SCI)
in SCI control register 1 (SCC1).
bit (TE) in SCI control register 2 (SCC2).
register 1 (SCS1) and then writing to the SCDR.
Serial Communications Interface Module (SCI)
Technical Data
215
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