STR912FW44X6 STMicroelectronics, STR912FW44X6 Datasheet - Page 66

• Manufacturer Part Number: STR912FW44X6
• Description: MCU 512K FLASH 96K SRAM USB CAN
• Manufacturer: STMicroelectronics
• Series: STR9r

Specifications of STR912FW44X6

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 96MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 2 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 128-LQFP
• For Use With: 497-8267 - BOARD EVAL BASED ON STR9MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2497-5859 - EVAL BRD FULL USB DONGLE STR912MCBSTR9 - BOARD EVAL STM STR9 SERIES
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: 497-5063-2; 497-5063-2; 497-5063-2ND; STR912FW44X6T

Electrical characteristics
6.14.5 SPI electrical characteristics
66/73
V
Table 29.
Figure 22. SPI slave timing diagram with CPHA=0
f
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCLK
r(SCLK)
f(SCLK)
su(SS)
h(SS)
w(SCLKH)
w(SCLKL)
su(MI)
su(SI)
h(MI)
h(SI)
a(SO)
dis(SO)
v(SO)
h(SO)
v(MO)
h(MO)
DDQ
Symbol
c(SCLK)
MISO
MOSI
= 2.7 - 3.6V, V
NSS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
SPI electrical characteristics
SPI clock frequency
SPI clock rise and fall times
SS setup time
SS hold time
SCLK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
DD
t
a(SO)
t
su(NSS)
Parameter
t
su(SI)
= 1.65 - 2V, T
t
t
MSB IN
w(SCLKH)
w(SCLKL)
MSB OUT
t
t
A
h(SI)
c(SCLK)
= -40 / 85 °C unless otherwise specified.
t
Master
Slave
50pF load
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable
edge)
Master (before capture
edge)
v(SO)
Test Conditions
BIT6 OUT
BIT1 IN
t
h(SO)
t
t
r(SCLK)
f(SCLK)
0.25
0.25
Typ
1
1
1
5
6
0
LSB IN
Value
0.1
LSB OUT
t
h(NSS)
Max
24
4
6
6
6
STR91xF
t
dis(SO)
t
MHz
Unit
V/ns
PCLK